SSE 3.0, SSE 4.2 in visual studio 2010 ultimate

[arrahul]

Hai

Please help me in enbaling the SSE 3 and SSE 4.2 in visual studio 2010 ultimate. I am currently working on a sandy bridge processor based desktopplatform running on win 7 SP1. The AVX option is getting enabled through /arch:AVX command line option, but not SSE options. I just have options of enabling SSE and SSE2, not higher versions. I tried with/QxAVX, /QaxAVX,/arch:SSE, /arch:SSE2...when I tried to compile the code , it is ignoring these options. It is just accepting /arch:AVX. I want the SSE 3.0 and higheroptionsto be enabled in this tool.Please help.

Thanks
Rahul

[Alexander_W_Intel]

Hi Rahul,

I think this is a double post: http://software.intel.com/en-us/forums/showthread.php?t=84683 . There you can already find an answer.

Thanks,
Alex

[zhou__patrick]

This problem solved?

[TimP]

If you are running a Visual Studio project, you must select Intel C++ in order to use Intel compiler and associated options.

When you made a similar post on Intel C++ forum, the assumption was that you had selected or at least installed Intel C++, but your post here leaves it in doubt.  Please choose a single forum most appropriate to your question.

VS2012 supports /arch:SSE2 and /arch:AVX, but not options which aren't applicable to AMD platforms.  I guess VS2010 may accept /arch:AVX but not do much useful with it.

[andysem]

AFAIK, MSVC doesn't generate any advanced SSE code (VS2012 is claimed to have a vectorizer, but I don't know how clever it is and what instruction set it uses). The /arch: switches mostly control how the floating point computations are compiled - to be performed by x87 FPU or SSE (the latter being the default). I think, /arch:AVX is mostly equivalent to /arch:SSE2, except it makes SSE code VEX-encoded, but I didn't verify that.

Anyway, unlike GCC, in MSVC all SSE/AVX intrinsics are available regardless of this compiler switch, you just have to include immintrin.h. It is your responsibility though to perform a CPU check and dispatch to the code version that suits the CPU.

[SergeyKostrov]

>>...when I tried to compile the code , it is ignoring these options. It is just accepting /arch:AVX... By the way, the user is right and this is what Microsoft C++ compiler help displays: cl.exe -help ... /arch: minimum CPU architecture requirements, one of: SSE - enable use of instructions available with SSE enabled CPUs SSE2 - enable use of instructions available with SSE2 enabled CPUs AVX - enable use of Intel(R) Advanced Vector Extensions instructions ... Please try to contact Microsoft's C++ compiler support.

[Bernard]

So there is no support of SSE3 and SSE4 instructions set? I thought that /arch:SSE2 switch means minimal ISA supported.

[SergeyKostrov]

>>...So there is no support of SSE3 and SSE4 instructions set? Yes as you can see. >>...I thought that /arch:SSE2 switch means minimal ISA supported. It means that SSE2 is supported ( take a look at MSDN ). By the way, I just found in MSDN the following statement: ... /arch is only available when compiling for the x86 platform. This compiler option is not available when compiling for x64 or Itanium. ...

[SergeyKostrov]

Rahul, Are you compiling your project for x86 or x64 platform?

[Bernard]

Thanks Sergey

[Sukruth_H_Intel]

Hi Rahul,

             Can i know what is the processor that you are using? Is it intel or non-intel processor? However you can install CPU-Z and see the  instructions specified by this tool. See if you have SSE3 and SSE4.x.

Regards,

Sukruth H V 

[Sukruth_H_Intel]

Hi Rahul,

             I am sorry i missed the word sandy bridge mentioned in the question. Let me investigate this and get back to you.

Regards,

Sukruth H V

[Sukruth_H_Intel]

Hi Rahul,

             So the issue here is that, You have not selected the Intel C++ compiler and you are using the Visual C++ compiler. Please select Intel C++ compiler and then goto Properties --> Code Generation [Intel C++] --> Intel Processor-Specific Optimization and then select the SIMD instruction set that you desire. This is what even Tim P wanted to convey.

Regards,

Sukruth H V