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I noted that on my Intel NH and AMD GH platforms.. the cpuid detection of sse 4.2 support is not found on AMD but is found on NH systems. I didn't know if you were aware of this.. does emulation of these instructions only occur upon systems with HW sse 4.2 support. I looked in the documentation and the cpuid detection bits are supposedly set to 1 in pin.. but still it is not observed to be set when I test.
Perfwise
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If I remember correctly, AMD does not support Intel's SSE4.2 instruction set apart from POPCNT instruction.
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Igor,
This is true.. but shouldn't pin/sde emulate the sse4.2 instructions just as they are doing for the AVX instructions. I just noted that on the AMD cpu.. it appears that the cpuid detection is not setting the support, within pin/sde, for SSE4.2. Don't know why.. if it's setting it for SSE 4.1, SSSE3, AES and AVX.
Perfwise
This is true.. but shouldn't pin/sde emulate the sse4.2 instructions just as they are doing for the AVX instructions. I just noted that on the AMD cpu.. it appears that the cpuid detection is not setting the support, within pin/sde, for SSE4.2. Don't know why.. if it's setting it for SSE 4.1, SSSE3, AES and AVX.
Perfwise
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Hi, I do not have any AMD systems to test upon, however, as far as I know nothing Intel SDE does depends on the manufacturer of the chip. By default, the STTNI emulation is enabled if the host hardware does not have STTNI support. In other words, I check the one CPUID bit for SSE4.2 (leaf 1, ecx[20]). If that is set to 1, then SDE does not enable the emulation. If it is set to 0, then the emulation occurs.
To force emulation on a chip that supports SSE4.2, you can use the knob "-sse42x". (You can see the numerous tool-specific knobs with "sde -thelp").
Your application or application compiler might be doing code selection based on other criteria and sending your program down another path. Or are you saying you see an illegal instruction error when you run under Intel SDE?

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