Intel® ISA Extensions
Use hardware-based isolation and memory encryption to provide more code protection in your solutions.
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This part of the documentation is ambiguous

This part of the documentation is ambiguous:
Intel software developer's manual, 3A:
-------------------------------------------------------------------- Protection of Exception- and Interrupt-Handler Procedures
The exception or interrupt handler can be placed in a conforming code segment.
This technique can be used for handlers that only need to access data available
on the stack (for example, divide error exceptions). If the handler needs data
from a data segment, the data segment needs to be accessible from privilege
level 3, which would make it unprotected.
What does it trying to say? Is it talking about an interrupt/exception handler with the privilege level 3?
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