What is the reason that VEX (and EVEX)-prefixed instructions are not supported in Real Mode and V86?
VEX-prefixed instructions (as well as LDS, LES instructions with the same opcodes too) work well in 16-bit Protected Mode, therefore it is logical to assume that it was technically possible to implement this support in Real Mode (and V86) too. But this is not implemented for some reason. I am extremely curious, what is the reason? :))
I read this topic: https://software.intel.com/en-us/forums/intel-isa-extensions/topic/297055. But there's no answer about the reason of #UD exception in RM.
- Intel® Advanced Vector Extensions (Intel® AVX)
- Intel® Streaming SIMD Extensions
- Parallel Computing