determining L1 and L2 cache state

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determining L1 and L2 cache state

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I apologize in advance if this has already been covered, but I'm trying to get worst case timing of some section of code and this requires all of L1 (data) and L2 cache to be dirty; of course L1 instruction cache to be invalid. I'm on a Core 2 Duo 8000 series.

I realize that all cache replacement algorithms are pseudo-LRU, but it would be very comforting to explicitly know for sure it's all dirty - in case I have an error in my dirtying code or something else is tampering with the cache.

I'm also aware that on the P6 family, there's the BBL_CR_CTL MSR that can do Tag inquiries, but this doesn't seem to be available for the Core 2 Duo.

Are there any instructions to get cache tag info, or are there any registers that will give this information? If not, any ideas?

Thanks for the help!
Matt

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