Intel® Integrated Performance Primitives
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What is the w7 processor type

DF
Beginner
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The following table was from the documentation but don't see w7 anywhere?

IA-32 Intel architecture

px

C-optimized for all IA-32 processors

v8

Optimized for processors with Intel Supplemental Streaming SIMD Extensions 3

p8

Optimized for processors with Intel Streaming SIMD Extensions 4.1

g9

Optimized for processors that support Intel Advanced Vector Extensions instruction set

s8

Optimized for the Intel Atom processor

Intel 64 architecture

mx

C-optimized for processors with Intel 64 instructions set architecture

u8

Optimized for 64-bit applications on processors with Intel Supplemental Streaming SIMD Extensions 3

y8

Optimized for 64-bit applications on processors with Intel Streaming SIMD Extensions 4.1

n8

Optimized for the Intel Atom processor

e9

Optimized for processors that support Intel Advanced Vector Extensions instruction set

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Ying_H_Intel
Employee
349 Views


Hi DF,

Thanks. I attached them here.
http://software.intel.com/en-us/articles/intel-integrated-performance-primitives-intel-ipp-understanding-cpu-optimized-code-used-in-intel-ipp/

The following table lists all the architecture codes defined by the Intel IPP library through version 6.1 of the product. Note that some of these IPP architectures have been deprecated and are no longer supported in the current version of the product. Deprecated architectures are identified in the Notes column of the table.

Platform

Architecture

SIMD Requirements

Processor / architecture

Notes

IA-32

px

C optimized for all IA-32 processors

i386+

a6

SSE

Pentium III

thru 5.3 only

w7

SSE2

P4, Xeon, Centrino

t7

SSE3

Prescott, Yonah

v8

Supplemental SSE3

Core 2, Xeon 5100, Atom

s8

Supplemental SSE3 (compiled for Atom)

Atom

new in 6.0

p8

SSE4.1, SSE4.2, AES-NI

Penryn, Nehalem, Westmere

see notes below

g9

AVX

Sandy Bridge architecture

new in 6.1

Intel 64 (EM64T)

mx

C-optimized for all Intel 64 platforms

P4

SSE2 minimum

m7

SSE3

Prescott

u8

Supplemental SSE3

Core 2, Xeon 5100, Atom

n8

Supplemental SSE3 (compiled for Atom)

Atom

new in 6.0

y8

SSE4.1, SSE4.2, AES-NI

Penryn, Nehalem, Westmere

see notes below

e9

AVX

Sandy Bridge architecture

new in 6.1

Itanium

i7

Intel Itanium processor family

Itanium

IXP4xx

sx

C-optimized for IXP4xx processors

IXP/XScale

thru 5.3 only

s2

IXP4xx optimized

IXP/XScale

thru 5.3 only


Best Regards,
Ying
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