64-bit atomic accesses

[a_boy_named_michael]

On a 64-bit machineis it safe to say that assignment to a 64-bit integer is atomic? In other words:

If 1 thread does this (C code):

unsigned __int64 a;

a = 1;

a = 0x200000000;

and another thread reads the value, it will read either 1 or 0x200000000, but never 0x200000001;

Does the address alignment of the variable matter? (i.e must that variable "a" be aligned to an 8 byte boundary?)

Is this the same on x64 versus Itanium platforms?

Thanks for any comments or pointers to a reference on this subject.

[robert-reed]

For ordinary memory accesses, which are to cached memory, it should never read 0x20000001, though it may have either of the two assigned values, or even the value before the first of the above assignments. Cached memory accesses are governed by the MESI protocol, which requires ownership of the cache line or lines (assuming you have an unaligned int64 bridging two adjacent cache lines). MESI guarantees on any particular write that the owner will be able to update memory before any other Processing Element can gain ownership of the cache line(s). That should be true for any processor that supports MESI cache coherence.

[loymaben]

nice post!!

[a_boy_named_michael]

Thanks for the excellent reply, although I have one follow up question.

I gather from limited research thatx64 and Itanium chips support MESI. However, I'm still trying to understand data alignment on Itanium systems. I read a good article on data alignment (http://msdn2.microsoft.com/en-us/library/aa290049.aspx) that indicates the Itanium does not provide hardware support for storing/fetching non-aligned 64-bit values. From my understanding the operating system must fixup the unaligned memory access by issuing 2 separate accesses. In this case, canan unaligned access that straddles a cache line boundary cause the 2 adjacent cache lines to become modified at different points in time?I would assume thattwoadjacent cache lines musttransition to the "modified" state at the exact same to to ensure that anotherprocessor's thread reads a consistent 64-bit value. Or is there another mechanism that ensures a consistent value?

Thanks again for any comments.

[TimP]

For Itanium, the only means for dealing with unaligned access is to eliminate it. No OS is obligated to support unaligned memory access.