About Adaptive Mode for L1 Cache in Hyper-threading

[zhaoguo_w_]

Dear all:

      I'm a student doing some research on Hyper-threading recently. I'm a little confused about the feature - L1 Data Cache Context Mode.

In the architecture optimization manual, http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html

It was described that L1 cache can operate in two modes:

The first level cache can operate in two modes depending on a context-ID bit:

Shared mode: The L1 data cache is fully shared by two logical processors.

Adaptive mode: In adaptive mode, memory accesses using the page directory is mapped identically across logical processors sharing the L1 data cache.

However, I am curious about how cache get partitioned in the adaptive mode according to the description.

Thanks~

[robert-reed]

You might find a better description of this in the systems programming guide, http://download.intel.com/products/processor/manual/253668.pdf The cache isn't so much partitioned as made available in its entirety to competitive caching from the two threads sharing it. The expectation when the CR3s of the two threads are different is that they are separate processes. When the CR3s are the same, the expectation is that they are shared threads within a process that might benefit from sharing cache lines--memory cached from one thread can be used from the cache by the other thread. This was an Intel Hyper-Threading Technology feature for the Intel Netburst architecture.