Cache Coherency problem on i5-520 and Xeon multi core

[smitra111]

Greetings,

We have some lock free code which use atomic CAS. That translates to "lock+cmpxchgl" instruction for x86 architecture. The code operates on multiple cores. We see that at times cache on different cores has stale entries, i.e., Core 0 has X but Core 1 has a previous value X'. At other times a transaction was lost as if the lock+cmpxchgl never happened. Has anyone faced such issues?

The ASM primitives used are:

[cpp]#define LOCK_PREFIX "lock;" #define atomic_cmpxchgl(mem, newval, oldval) \ ({ __typeof (*mem) ret; \ __asm __volatile (LOCK_PREFIX "cmpxchgl %2, %1" \ : "=a" (ret), "=m" (*mem) \ : "r" ((uint32_t) (newval)), "m" (*mem), \ "0" ((uint32_t) (oldval))); \ ret; }) [/cpp]

Usage in C code ...

[cpp] do { } while (atomic_cmpxchgl(&elem->hdr, CONSUMER_FREE, PRODUCER_BUSY) != PRODUCER_BUSY); [/cpp]
Any comments or pointers shall be appreciated.

Thanks,
Somnath Mitra.

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