Does each core on an intel multi-core processor have a separated full set of MSRs?

[Xuehan_X_]

Hi, everyone.

Does each core on an intel multi-core processor have a full set of MSRs that are separated from other cores?

[McCalpinJohn]

Each MSR has a "scope" that is listed in the various model-specific tables of Chapter 35 of Volume 3 of the Intel Architectures SW Developer's Guide (document 325384).

• MSRs with a scope of "thread" are separate for each logical processor and can only be accessed by the specific logical processor.
• MSRs with a scope of "core" are separate for each core, so they can be accessed by any logical processor (thread context) running on that core.
• MSRs with a scope of "package" are global to the package, so access from any core or thread context in that package will access the same register.

[Xuehan_X_]

John D. McCalpin wrote:

Each MSR has a "scope" that is listed in the various model-specific tables of Chapter 35 of Volume 3 of the Intel Architectures SW Developer's Guide (document 325384).

• MSRs with a scope of "thread" are separate for each logical processor and can only be accessed by the specific logical processor.
• MSRs with a scope of "core" are separate for each core, so they can be accessed by any logical processor (thread context) running on that core.
• MSRs with a scope of "package" are global to the package, so access from any core or thread context in that package will access the same register.

Thanks for your reply, sir:-)

I checked the model-specific tables you mentioned and found that only MSRs that used for some global functions, like SpeedStep or CPU TDP and so on, are designed with a scope of "package". And since each core has a completely independent(not shared with other cores) set of registers except for these MSRs, I guess that all hardware control structures that are not designed for those global functions are not shared among cores, even the VMX related control structures. Is that right?

Thanks, sir:-)

[agnes_m_]

The same function talks about AMD, but what about Intel? ... column “Shared/Unique” applies to multi-core processors based on Intel Core microarchitecture. “Unique” means each processor core has a separate MSR, or a bit ... If it is marked as package then the MSR is shared across the entire processor.  http://www.trainingintambaram.in/php-training-in-chennai.html  | http://www.trainingintambaram.in/web-designing-training-in-chennai.html

[McCalpinJohn]

Xuehan -- I am not exactly sure I understand your question.  It may help to be more specific about the processor that you are interested in....

The tables in Chapter 35 of the Intel Architecture SW Developer's manual are pretty clear about the scope of the MSRs except in three cases.

1. The table of "architectural" MSRs does not include the "scope" field.  Fortunately most of these MSRs are also listed in the model-specific tables.  The description of the MSR in these tables typically points back to the table of "archtitectural" MSRs, but the scope is listed in the model-specific table.
2. Some of the tables use the nomenclature "shared" vs "unique" instead of "core" vs "thread".  This includes the Atom and Pentium 4 tables.
3. Some of the tables use the nomenclature "shared" vs "unique" instead of "package" vs "core".  This includes the Core Duo and Core 2 tables. 

In the latter two cases the use of the term "unique" is described fairly clearly either in the introduction to the model-specific table or in the footnotes to the table.

[Xuehan_X_]

John D. McCalpin wrote:

Xuehan -- I am not exactly sure I understand your question.  It may help to be more specific about the processor that you are interested in....

The tables in Chapter 35 of the Intel Architecture SW Developer's manual are pretty clear about the scope of the MSRs except in three cases.

1. The table of "architectural" MSRs does not include the "scope" field.  Fortunately most of these MSRs are also listed in the model-specific tables.  The description of the MSR in these tables typically points back to the table of "archtitectural" MSRs, but the scope is listed in the model-specific table.
2. Some of the tables use the nomenclature "shared" vs "unique" instead of "core" vs "thread".  This includes the Atom and Pentium 4 tables.
3. Some of the tables use the nomenclature "shared" vs "unique" instead of "package" vs "core".  This includes the Core Duo and Core 2 tables. 

In the latter two cases the use of the term "unique" is described fairly clearly either in the introduction to the model-specific table or in the footnotes to the table.

Sorry, sir:-)

I didn't make myself clear. Actually, I'm considering the possibility to run multiple VMMs on one single physical machine, I think that if each processor core has a complete and independent set of the hardware control structures, including registers and other logic circuits, that are necessary to run a VMM, then running multiple VMMs on one single processor should be possible. So, I asked this question. Thank you:-)

[jimdempseyatthecove]

This would be dependent upon the Hypervisor.

If the hypervisor never oversubscribes the number of hardware threads then there will be no requirement for the hypervisor to time slice (and subsequently context switch the register contexts) the VM.

However, if the hyper does oversubscribe the number of hardware threads (time slices the VMs) then it will be required to context switch the registers in the VM.

Jim Dempsey

[McCalpinJohn]

What Jim said....