Interrupts - Lowest priority mode and the LDR

[a_s_1]

Hopefully this is the right forum for this question... I'm seeking clarification on how lowest priority mode works with the values programmed into the xAPIC's Logical Destination Register. Simply put, my question is: if I program multiple CPU's LDR identically, and set up the I/O APIC for an interrupt to use lowest priority delivery mode, logical destination mode, and a destination to match that of the LDR of multiple CPUs, when the interrupt is triggered, should all of the CPUs (local APICs) who's LDR matches arbitrate amongst themselves to decide which one actually handles the interrupt? What I'm seeing on some machines is that the interrupt is being handled by all of the CPUs that share that LDR value, not just one. I only see this, however, on some of my server hardware. Desktop machines, including Virtual Box behave as I would expect. My setup: Processor: Intel® Xeon® Processor E5-2667 v4 Chipset: c612 - I've disabled x2APIC in the BIOS, and my OS doesn't use/implement support for x2APIC - During boot I set the logical destination register (LDR) of the boot APIC to be 0x01 << 24 - When configuring the I/O APIC, I set the appropriate redirection table entries to 0x0100000000000936, which should be lowest priority, logical mode. - When I bring up all of the application processors, I set all of their LDR's to be 0x02 << 24 - Once all APs are up, I update all of the I/O APIC table registers to be: 0x0300000000000936 - At boot, I set the TPR to 0 for all local APICs, and don't touch it again after. - The Destination Format Register is set to use the flat model (high 4 bits all 1's) for all local APICs I've not seen anything in the Intel Developers manual that suggests there's a difference in how the Xeon processors handled lowest priority interrupts, so any help or insight you all could provide would be much appreciated. Thanks!

[SergeyKostrov]

>>...What I'm seeing on some machines is that the interrupt is being handled by all of the CPUs that share that >>LDR value, not just one... I wonder how is it possible? Do you mean just one interrupt or a series of interrupts, let's say 64? An interrupt handler is Not a regular ( let's say Win32, or Posix, or anything else ) thread. It seems to me that you're observing some kind of Interrupt Handler thread migration ( hard to believe in that! ), that is, similar to a regular thread migration when a thread affinity is Not set at the beginning of processing and, in that case, an Operating System does what it wants and it does Not do what a developer wants.

[a_s_1]

I'm developing an OS, so this isn't an application. Suspect this isn't the right forum, but I don't see anything appropriate for low-level OS development / architecture questions.

For testing purposes, I've programmed the PIT to generate a single interrupt and what I'm seeing is that multiple LAPICs accept the interrupt and execute the programmed IDT handler... Seems for these systems, I should really be using clustering - flat mode doesn't seem to work.

[JWong19]

You may ask additionally in https://communities.intel.com/community/tech/processors and describe the indifferent behavior (saying suspected bug) of this processor. Let's see if they would find you the right persons for the answer.

Programming APs is an interesting urban area, but I don't find a strong excuse to have the APs servicing interrupts when we already have windows and linux......

[SergeyKostrov]

>>...I've programmed the PIT to generate a single interrupt and what I'm seeing is that multiple LAPICs accept >>the interrupt and execute the programmed IDT handler... I'll take a look at my very old software engineering notes related to that subject but I can't promise a quick response. PS: I wanted to ask you about an OS but you've finally answered that it is your own OS.

[SergeyKostrov]

>>...but I don't find a strong excuse to have the APs servicing interrupts when we already have windows and Linux... There are hundreds of different OSs designed and developed during last 30-40 years and these R&Ds will never stop. Some OSs are highly customized, Hard Real-Time, etc. I don't see anything wrong with it... PS: How many new models of cars released every year?.. Many. Almost the same applies to the Software Engineering.