Community
cancel
Showing results for 
Search instead for 
Did you mean: 
srimks
New Contributor II
63 Views

WAR & WAW - Intel 16-stage pipeline?

Hello,

Wish to know - Can WAR & WAW happen in current Intel Multi-core architecture (MCA) processor having 16-stage pipeline?

~BR
0 Kudos
3 Replies
Thomas_W_Intel
Employee
63 Views

Quoting - srimks
Hello,

Wish to know - Can WAR & WAW happen in current Intel Multi-core architecture (MCA) processor having 16-stage pipeline?

~BR

On current Intel processors, a WAR (write-after-read) hazard cannot happen, because writes are not reordered with older reads. A WAW (write-after-write) issue can happen under certain circumstances, because writes can be reordered with other writes executed with the CLFLUSH instruction, streaming stores,or string operations.
For further details, please refer to theIntel 64 and IA-32 Architectures Software Developers Manual, Volume 3A, Section 7.2.2.

Kind regards
Thomas
srimks
New Contributor II
63 Views


On current Intel processors, a WAR (write-after-read) hazard cannot happen, because writes are not reordered with older reads. A WAW (write-after-write) issue can happen under certain circumstances, because writes can be reordered with other writes executed with the CLFLUSH instruction, streaming stores, or string operations.
For further details, please refer to the Intel 64 and IA-32 Architectures Software Developers Manual, Volume 3A, Section 7.2.2.

Kind regards
Thomas
Really appreciate for clarifying. The section does descibes complete behaviour of WAR & WAW as asked.

~BR
Mukkaysh Srivastav
srimks
New Contributor II
63 Views


On current Intel processors, a WAR (write-after-read) hazard cannot happen, because writes are not reordered with older reads. A WAW (write-after-write) issue can happen under certain circumstances, because writes can be reordered with other writes executed with the CLFLUSH instruction, streaming stores,or string operations.
For further details, please refer to theIntel 64 and IA-32 Architectures Software Developers Manual, Volume 3A, Section 7.2.2.

Kind regards
Thomas

Hello Thomas,

Could you share the links for other Intel latest (March'2009) documents like - Intel Arch. Opt. Manual, Vol1 & Vol2 Inst. Manual, SPG-3B, etc.

I do have older(2007-2008) ones.

~BR
Reply