Intel® Moderncode for Parallel Architectures
Support for developing parallel programming applications on Intel® Architecture.

atomic accesses

_ace_
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System Programming Guide 3A says:

Section 7.1.1
>> Unaligned 16-, 32-, and 64-bit accesses to cached memory that fit within a cache line

Does this really mean "cached memory" or is the intent here "cacheable memory", as if it is intended to be cached memory then it does not give much to application programmers, does it?



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