I have 2 questions:
DP system with 2 woodcrest processors,
core 0 and core 1 are on CPU 0
and core 2 and core 3 are on CPU 1
if core 0 need memory data that is cached in core 3, what will the Northbridge or memory controller do?
DP system with 2 clowverton processors,
core 0, 1, 2 and 3 are on CPU 0; core 0 and 1 share the L2 cache.
core 4, 5, 6 and 7 are on CPU 1; core 4 and 5 share the L2 cache.
what will the Northbridge or memory controller do when core 0 need memory data that is cached in core 7? The last and most import questions for me:how about if core 0 need data that is cached in core 2? They are on the same CPU package but dosen't share L2 cache, does Northbridge need to interven the transcation?
Thanks for your answer in advance.