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加法器进位链

xuanzi
Beginner
273 Views
大家好,我最近用加法器构造进位链,出来的波形可以看到进位链没有形成,我想请问一下,如何让fpga中的LE工作在算术模式下,在我的程序中,查看底层,好像没有使用cin到cout,而是使用查找表,我想问一下怎么设置才能使用LE的进位链;我还想问一下,如何设置quartus软件,让它不优化我的电路。
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6 Replies
xuanzi
Beginner
250 Views

谢谢您的回复。我使用了加法器ip构造出延迟链,但是出来的延迟结果,好像不是很均匀,我想请问下这是什么原因。    祝您工作顺利!

xuanzi_0-1603502455342.png

 

 

 

KhaiChein_Y_Intel
239 Views

Hi,


May I know what device you are using?


Thanks

Best regards,

KhaiY


xuanzi
Beginner
238 Views

你好:

    我使用的FPGA 是cyclone III EP3C16F484C6N

KhaiChein_Y_Intel
231 Views

Hi,


According to Intel Quartus Prime Standard Edition User Guide: Third-party Simulation https://www.intel.com/content/www/us/en/programmable/documentation/gtt1529956823942.html, Gate-level timing simulation is supported only for the Arria® II GX/GZ, Cyclone® IV, MAX® II, MAX® V, and Stratix® IV device families. Kindly use Timing Analyzer static timing analysis rather than gate-level timing simulation.


Thanks

Best regards,

KhaiY


KhaiChein_Y_Intel
220 Views

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY


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