HelloFor my project I need 0to16 counter with 2 additional inputs: reset singal sets the counter to 0, other one sets the counter to 8. I simulated my idea in simply application logisim and it worked very nice. However, I can't implement it in Quartus II. https://www.alteraforum.com/forum/attachment.php?attachmentid=6681 It counts from 0to16, but no reset nor eight signal affect it's work. What's more, version with only one reset signal (no "eight", no OR gates) works. According to this data: quartushelp.altera.com/9.1/mergedProjects/hdl/prim/prim_file_jkff.htm the counter should also work. Help me please find out what is the mistake.
Two points:- the logic needs AND rather than OR gates to combine the reset signals. - asynchrounous set/reset are simple to implement but rather problematic in operation. You have to assure that set/reset takes place with sufficient separation to clock edges.