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2 bit carry ripple carry adder delay problem

Altera_Forum
Honored Contributor II
‎03-25-2013 02:27 AM
1,553 Views

I am working on 2 bit carry using component FA .Each gate has delay 2nsec.Expected delays for carry out =8nsec,so =2 nsec ,s1=6 nsec.but i am getting s0=2nsec,s1=6nsec and carry=4nsec. The code and test bench waveform is with attachment.I am using xilinx 9.1i

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Altera_Forum
Honored Contributor II
‎03-25-2013 02:40 PM
842 Views

I think you are in wrong forum.

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