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Dear Sir,
I had a SPI_master question needs to be confirmed.
For my system, one sys_clk is 50MHz used for main clock and that SPI_master sck_o sync with sys_clk to output.
Could I apply another clock (latch_clk) that shift -120 with sys_clk (applied from PLL) to latch spi input data?
I would like to increase the setup/hold time and cover the pcb delay.
And, does any advantages/disadvantage for this architecture?
Btw, this spi_master works at CPOL=1 and CPHA=1 mode for now.
Please let my know if any opinion for this.
Thank you very much.
Josh
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Hi,
What is the frequency latch_clk?
Thanks.
Best regards,
KhaiY
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Hi,
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
Best regards,
KhaiY

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