4bit siso shift register

[Altera_Forum]

I used the following code for 4bit siso shift register. 

  Signal temp : std_logic_vector( 3downtown 0); begin process begin if(rising_edge(clk)) then temp(3 downtown 1)<=temp(2 downto 0); temp(0)<=si; end if; end process; so<=temp(3); end behavioural;   I used the following testbench code. clk<= '0'; si<='1'; wait for 100ns;  clk<= '1'; si<='1'; wait for 100ns;  But after stimulation its shows that so is undefined i.e a red bar is shown.... Pls help......

[Altera_Forum]

You only show a single clock in the testbench code. It will take 4 clocks for si to propogate to so.

[Altera_Forum]

clk<= '0'; 

si<='1'; wait for 100ns;  clk<= '1'; si<='1'; wait for 100ns; clk<= '0'; si<='1'; wait for 100ns;  clk<= '1'; si<='1'; wait for 100ns; clk<= '0'; si<='1'; wait for 100ns;  clk<= '1'; si<='1'; wait for 100ns; clk<= '0'; si<='1'; wait for 100ns;  clk<= '1'; si<='1'; wait for 100ns; I have used the above coding..... Even if I use 4 clocks its still shows the red bar

[Altera_Forum]

Pls help.....

[Altera_Forum]

Please post all of your code, not just an extract.

[Altera_Forum]

did you try to initialize temp(3 downto 0) to an initial value? If not you need at least 4 clock edges to get "so" "green" 

if "red" it would be that you never put anything on it...

[Altera_Forum]

AND , you have to put "clock" in the process sensitivity list....