7.2sp1 cant produce working sof

[Altera_Forum]

I am using a CII dev board with Q7.2sp1 web edition. 

 The PLL in my Q7.2 niosII project seemed to stop working after some unrelated mods, so I installed Q7.2sp1 thinking it might help. I created a new BDF based project from scratch with just a PLL and some IO as a test.   I have two external clocks which feed the fpga. I have one of them going straight from the input to an output pin using a wire connection, and the other thru a pll to an output pin. The project builds but the sof does nothing. There is nothing on either output.   I cannot understand how a simple wire connection could fail. It behaves like my pin assignments or device are wrong, but they are not. I can take a reference design I built a week ago, which uses those same pins and PLL, and the original sof works, but a new one doesn't.

[Altera_Forum]

The problem was the device setting "reserve unused pins as outputs tied to ground". After reading the many posts on this, I can see it is one of the biggest time-wasters in quartus. It might be useful if it did what it said, but as far as I can tell this setting ties ALL usable pins to gnd, including the ones you have assigned as IO.  

 The feature should be renamed to "break my project, waste my time".

[Altera_Forum]

Hello, 

 I agree that "reserve unused pins as outputs tied to ground" could cause problems and probably shoulnd't been choosed as Quartus default option by Altera. But I think, it doesn't touch pins assigned otherwise. The issue is with pins having a particular hardware function but are yet unassigned in Quartus design. For this reason, I use "input with weak pullup" option (but sometimes, I may forget to change the option).  Regards,  Frank

[Altera_Forum]

--- Quote Start ---  I agree that "reserve unused pins as outputs tied to ground" could cause problems and probably shoulnd't been choosed as Quartus default option by Altera. But I think, it doesn't touch pins assigned otherwise. The issue is with pins having a particular hardware function but are yet unassigned in Quartus design. For this reason, I use "input with weak pullup" option (but sometimes, I may forget to change the option).  --- Quote End ---     The default is better for new device families. For a new Cyclone III or Stratix III project in QII 7.2 SP1, the default is "As input tri-stated with weak pull-up resistor".  I prefer "As input tri-stated with bus-hold circuitry" so that the default is suitable for unused I/O grounded on the board without wasting current through a weak pull up.  If your preferred project-wide default isn't suitable for all pins like a few that are grounded on the board, change the setting for individual unused I/O pins by using the "Reserve Pin" setting in the Assignment Editor or Pin Planner.

[Altera_Forum]

You guys seem to think that the setting, "as output tied to gnd" can actually be used without breaking a project. I am telling you that it can't. Try creating a simple project as I did with just one input and one output. Use a bdf, not hdl. If you can get the output to do anything other than sit at gnd (without changing the "output tied to gnd" setting), then your install is behaving differently from mine. Now try to explain how it could ever be useful.

[Altera_Forum]

As Frank indicated, setting "Reserve all unused pins" to "As output driving ground" (or to anything else) affects only the I/O pins that do not have a signal in your design--either a source file top-level port or an individual pin reserved with the "Reserve Pin" setting--placed at them. I have never seen the behavior you described. If you haven't yet, check the .pin file or the Fitter compilation report pin tables to confirm that the signals in your source file were actually placed at the pin locations you intended. If the signals were at the correct pin, then I suggest that you file a service request to find out whether you've run into a bug or have something else going on that you haven't uncovered yet.

[Altera_Forum]

Hello, 

 I tried with V7.2 (I didn't yet install SP1) without doing pin assigments, so the fitter picked input and output pins. From the Pin-Out File, the "design" looks functional.  pin_name1 : 57 : output : 3.3-V LVTTL : : 4 : N  pin_name : 58 : input : 3.3-V LVTTL : : 4 : N  GND* : 59 : : : : 4 :  GND* : 60 : : : : 4 :   Also when assigning pin locations explicitely in Pin Planner, anything seems to be correct. I don't think there is a difference between HDL or BDF input. Could it be that SP1 behaves different?  Regards,  Frank