7 segment display

Altera_Forum · ‎10-24-2013

Hi all.

I have problem to display "HELLO" on 7 segment display. Even though my vhdl code is successful, but its only display "H" on HEX0. Here is my code. I want to display "HELLO" on 7 segment. "H" on HEX0, "E" on HEX1, "L" on HEX2, "L" on HEX3, "O" on HEX4. Do you have any ideas regarding my problem. Thanks in advance

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY part5 IS

PORT ( SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0);

HEX0,HEX1,HEX2,HEX3,HEX4 : OUT STD_LOGIC_VECTOR(0 TO 6));

END part5;

ARCHITECTURE Behavior OF part5 IS

COMPONENT mux_3bit_5to1

PORT ( S, U, V, W, X, Y : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

M : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));

END COMPONENT;

COMPONENT char_7seg

PORT ( C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

Display : OUT STD_LOGIC_VECTOR(0 TO 6));

END COMPONENT;

SIGNAL M : STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN

M0: mux_3bit_5to1 PORT MAP (SW(17 DOWNTO 15), SW(14 DOWNTO 12), SW(11 DOWNTO 9), SW(8 DOWNTO 6), SW(5 DOWNTO 3), SW(2 DOWNTO 0), M);

H0: char_7seg PORT MAP (M,HEX0);

END Behavior;

LIBRARY ieee;

use ieee.std_logic_1164.all;

ENTITY mux_3bit_5to1 IS

PORT ( S, U, V, W, X, Y : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

M : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));

END mux_3bit_5to1;

ARCHITECTURE Behavior OF mux_3bit_5to1 IS

begin

Behavior: with S select

M <= U when "000",

V when "001",

W when "010",

X when "011",

Y when "100",

Y when "101",

Y when "110",

Y when "111";

END Behavior;

LIBRARY ieee;

use ieee.std_logic_1164.all;

ENTITY char_7seg IS

PORT ( C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

Display : OUT STD_LOGIC_VECTOR(0 TO 6));

END char_7seg;

ARCHITECTURE Behavior OF char_7seg IS

signal input : std_logic_vector (2 downto 0);--define input bit

signal output : std_logic_vector ( 6 downto 0);--define output bit

begin

input <= C;

with input select

Display <= "1001000" when "000" ,

"0110000" when "001",

"1110001" when "010",

"0000001" when "011",

"1111111" when others;

end Behavior;

Altera_Forum · ‎10-24-2013

You have 4 output vectors so:

HEX0 <= "0110000";

HEX1 <= "1110001";

HEX2 <= "0000001";

HEX3 <= "1111111";

Altera_Forum · ‎10-24-2013

The behaviour you observe is correct, since you are NOT driving HEX1 to HEX4 lines, but only HEX0.

Although I don't know if this is really what you mean to do, I suggest you replace the line

H0: char_7seg PORT MAP (M,HEX0);

with:

char_7seg PORT MAP (SW(14 DOWNTO 12),HEX0);

char_7seg PORT MAP (SW(11 DOWNTO 9),HEX0);

char_7seg PORT MAP (SW(8 DOWNTO 6),HEX0);

char_7seg PORT MAP (SW(5 DOWNTO 3),HEX0);

char_7seg PORT MAP (SW(2 DOWNTO 0),HEX0);

Altera_Forum · ‎10-25-2013

Thanks bertulus and Cris72 for your suggestion. Have solve it.