A/D converter-FPGA-USB

[Altera_Forum]

Hello, 

 can anybody provide some basic idea to get digital data from A/D converter(HSMC) into cyclone IVE fpga and pass it into computer via USB port.  Thanks in advance

[Altera_Forum]

--- Quote Start ---   can anybody provide some basic idea to get digital data from A/D converter(HSMC) into cyclone IVE fpga and pass it into computer via USB port.   --- Quote End ---    Not really, your questions are too vague.  1) What ADC? How many bits and at what speed does it operate?  2) Which version of USB - 1.0 (12Mbps), 2.0 (480Mbps), or 3.0 (5Gbps)?  3) Do you have a specific board in mind? Since you mention HSMC, its likely you already have a board.  Provide this information and you'll get more help.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Not really, your questions are too vague.  1) What ADC? How many bits and at what speed does it operate?   --- Quote End ---    -->Highspeed AD/DA Card made by terasic for HSMC: 14-bit resolution and data rate up to 65 MSPS.   http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=73&no=278&partno=1  and I want to use it as Analog to digital converter. Although there are data pin configuration given in its user manual I am not sure about control pins how to map.   --- Quote Start ---   2) Which version of USB - 1.0 (12Mbps), 2.0 (480Mbps), or 3.0 (5Gbps)?   --- Quote End ---   -->In the user manual of DE2-115, it is given that: USB rev. 2.0 data transfer at full speed(12 Mbps) and low speed(1.5 Mbps).  and I want to operate it at full speed(12 mbps)   --- Quote Start ---   3) Do you have a specific board in mind? Since you mention HSMC, its likely you already have a board.   --- Quote End ---   -->The board I already have is DE2-115 (Cyclone IVE).  http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=139&no=502   --- Quote Start ---   Provide this information and you'll get more help.  Cheers, Dave  --- Quote End ---    -->Thanks for your response and further infos are available above :)

[Altera_Forum]

****! i was unable to quote in previous reply. this is the proof of new user :). any way, asked info is available within the quote

[Altera_Forum]

I reformated your post to remove your answers from the "quote" part, which makes them easier to read. I hope you don't mind ;) 

 If you go in "resources" on the terasic web page for the AD/DA board, you can download a CD image. This CD probably has some example designs, and even if they don't seem to be made for the DE2-115, you can still see how they interfaced the AD/DAs and reuse some of the code or components in your own design.

[Altera_Forum]

Thanks for the suggestion. 

I got the pin configuration for ADC available in my board CD of daughter card(AD/DA).  The pin configuration given in that CD even matches with the Pin configuration I generate using "DE2-115 system builder" by selecting clock and HMSC high speed A/D card which I am using currently.  But when I look for pin configuration for HSMC on User Manual of DE2-115, It doesn't match with previous one I mentioned. So, I am a afraid of using it like may be it damage the board.

[Altera_Forum]

There is also one Verilog example within the CD of daughter card: 

module DE2_115_ADDA(   //////// CLOCK //////////  CLOCK_50,  CLOCK2_50,  CLOCK3_50,   //////// I2C for HSMC //////////  I2C_SCLK,  I2C_SDAT,   //////// HSMC //////////  ADC_CLK_A,  ADC_CLK_B,  ADC_DA,  ADC_DB,  ADC_OEB_A,  ADC_OEB_B,  ADC_OTR_A,  ADC_OTR_B,  DAC_CLK_A,  DAC_CLK_B,  DAC_DA,  DAC_DB,  DAC_MODE,  DAC_WRT_A,  DAC_WRT_B,  OSC_SMA_ADC4,  SMA_DAC4  );  //======================================================= // PORT declarations //=======================================================  //////////// CLOCK ////////// input CLOCK_50; input CLOCK2_50; input CLOCK3_50;  //////////// I2C for HSMC ////////// output I2C_SCLK; inout I2C_SDAT;  //////////// HSMC ////////// output ADC_CLK_A; output ADC_CLK_B; input [13:0] ADC_DA; input [13:0] ADC_DB; output ADC_OEB_A; output ADC_OEB_B; input ADC_OTR_A; input ADC_OTR_B; output DAC_CLK_A; output DAC_CLK_B; output [13:0] DAC_DA; output [13:0] DAC_DB; output DAC_MODE; output DAC_WRT_A; output DAC_WRT_B; input OSC_SMA_ADC4; input SMA_DAC4;  I was not able to add complete code due to following errors: You have included 7 images in your message. You are limited to using 4 images so please go back and correct the problem and then continue again.     As I am going to use only one channel out of 4(ADC_DA) for my purpose(Analog to digital conversion), I will map the 14 bit data pins of FPGA with this one. but I am not sure about which other pins like clock, OTR,OEB, etc will be needed for my purpose.  For first step i am planning to take the signal from AD converter and display corresponding output into red led like this: library ieee; use ieee.std_logic_1164.all;  ENTITY part1 IS PORT ( ADC_DA : IN STD_LOGIC_VECTOR(13 DOWNTO 0); LEDR : OUT STD_LOGIC_VECTOR(13 DOWNTO 0) );  END part1; ARCHITECTURE Behavior OF part1 IS BEGIN LEDR <= ADC_DA; END Behavior;   can anybody make me clear.

[Altera_Forum]

--- Quote Start ---   But when I look for pin configuration for HSMC on User Manual of DE2-115, It doesn't match with previous one I mentioned. So, I am a afraid of using it like may be it damage the board.  --- Quote End ---    What are the differences that concern you?  So long as the pin numbers correspond to pins on the connector, the names do not matter.  Look at the schematic of the DE115 and create a table of the net names used in the schematic and the corresponding FPGA pin number. Then add a column for the two different pinouts you have. That will help confirm that the names used in the VHDL examples map to pins that are GPIO.  Successful synthesis with Quartus will also tell you that the pin assignments are valid. However, it will not tell you that the pins you have used actually route to the GPIO header - since that is board specific.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  There is also one Verilog example within the CD of daughter card: module DE2_115_ADDA ...   --- Quote End ---    Don't post code inline in messages. It just clutters the forum. There is a "Manage Attachments" button that can be used to add code.    --- Quote Start ---   For first step i am planning to take the signal from AD converter and display corresponding output into red led like this:   --- Quote End ---    Your first step should be to connect the clock and data to the GPIO and use SignalTap to capture a trace of data. SignalTap is an FPGA logic analyzer. Using that interface, you will be able to see what outputs from the DAC do when you control inputs.  Actually, your first step should be to run a Terasic example design. I am sure they must have one. If you cannot find one, contact them and ask for one.  Cheers, Dave

[Altera_Forum]

What is the relation between clock and data rate of digital device(e.g. ADC in my case)?? 

 The ADC of daughter card support up to 65 MSPS(mega sample per second). Does it mean that we can use clock frequency less than 65 MHZ(lets say 50 MHZ or 2 MHZ) but can't use clock frequency greater than 65 MHZ (lets say 100 MHZ) to get output??  I used frequency 100 MHz from its oscillator and didn't get any output.

[Altera_Forum]

@dwh@ovro.caltech.edu:: I am using ADA_HSMC instead of GPIO as my daughter card only support HSMC. 

 Although using HSMC it doesn't make any difference to GPIO while capturing signal with Signal Tap if pin is mapped for HSMC instead of GPIO. Isn't it??

[Altera_Forum]

--- Quote Start ---  What is the relation between clock and data rate of digital device(e.g. ADC in my case)??  The ADC of daughter card support up to 65 MSPS(mega sample per second). Does it mean that we can use clock frequency less than 65 MHZ(lets say 50 MHZ or 2 MHZ) but can't use clock frequency greater than 65 MHZ (lets say 100 MHZ) to get output??  I used frequency 100 MHz from its oscillator and didn't get any output.  --- Quote End ---    A "65MHz ADC" can be clocked at up to 65MHz. 100MHz is too high. You can also clock it at lower frequency.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  I am using ADA_HSMC instead of GPIO as my daughter card only support HSMC.   Although using HSMC it doesn't make any difference to GPIO while capturing signal with Signal Tap if pin is mapped for HSMC instead of GPIO. Isn't it??  --- Quote End ---    As far as the FPGA is concerned, the two interfaces are the same; they connect to pins on the FPGA.  You can use SignalTap in both cases.  Cheers, Dave

[Altera_Forum]

Hi, thanks for the reply. 

 So, can we say that ADC having maximum datarate 65 MSPS(mega sample per second) means it indirectly saying maximum frequency that it can support(here 65 MHZ)?  i.e. Data rate corresponds to frequency it supports. am i right??  and sorry if my question is so obvious.

[Altera_Forum]

--- Quote Start ---   So, can we say that ADC having maximum datarate 65 MSPS(mega sample per second) means it indirectly saying maximum frequency that it can support(here 65 MHZ)?  i.e. Data rate corresponds to frequency it supports. am i right??   --- Quote End ---    There's several terms you need to use when thinking about ADCs  1) Sampling rate  This is the rate at which the analog signal is sampled. It is also typically the same as the clock rate. However, some devices have internal PLLs that define the clock rate, and so the external clock rate is not the same as the sample rate.  2) Data rate  Some ADCs output data at the same rate as their sample rate. Higher frequency parts include demultiplexing, so output wider data buses at a lower rate than the sample rate. Other ADCs multiplex the samples onto serial data streams (JEDEC JESD204) so the output data rate is higher than the clock rate.  3) Analog bandwidth  Many ADCs are used for sampling a band of frequencies. That band of frequencies can lie in a Nyquist zone, where a zone is a band with bandwidth of under fs/2. For example, the first Nyquist zone is at DC to fs/2, the second is fs/2 to fs, and the third is fs to 3fs/2. These types of ADCs are called IF sampling or direct conversion ADCs. They save you a downconversion by using aliasing to get the signal to baseband.  Read the data sheet for your ADC board and the data sheet for the ADC IC on the board, and you'll find these terms, or terms very similar to this.  Cheers, Dave

[Altera_Forum]

What have you setup for the clock source? 

 Page 2 of the schematic has the ADC. There is a POWERON signal, and ADC_CLKA and ADC_CLKB clocks. Have you got something driving those signals?  The ADC_CLKA and ADC_CLKB signals come from the headers JP1 and JP2. Which jumper do you have attached?  Do you have an input signal attached? If you do not, then the ADC will sample whatever the center tap value is. Assuming the ADC outputs in 2's compliment format, that could be zero (0) or all ones (-1).  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  What have you setup for the clock source?  --- Quote End ---    I tried in following 2 ways and none of them worked:  1. using the 100 MHZ oscillator of daughter card by setting jumper between 3 & 4 of JP1 as given in schematic. 2. using the oscilltor of FPGA board having 50 MHZ and map this signal with ADC_CLK_A as a PLL. and in this case setting jumper between 1 & 2 of JP1 as given in schematic.    --- Quote Start ---  Page 2 of the schematic has the ADC. There is a POWERON signal, and ADC_CLKA and ADC_CLKB clocks. Have you got something driving those signals?   --- Quote End ---    I didn't find any setting for POWERON signal. For ADC_CLK_A, I used as described above in 1 & 2. For ADC_CLK_B: As i am using only one channel (Channel A), So, I think it will not be necessary.     --- Quote Start ---  The ADC_CLKA and ADC_CLKB signals come from the headers JP1 and JP2. Which jumper do you have attached?  --- Quote End ---   JP1 setting is described above and JP2 setting I don't need it as I am using only one channel (channel A).    --- Quote Start ---  Do you have an input signal attached? If you do not, then the ADC will sample whatever the center tap value is. Assuming the ADC outputs in 2's compliment format, that could be zero (0) or all ones (-1).  --- Quote End ---    yes, I have attached the input signal.   I guess I also have to set some control signals for these two:: "I2C for HSMC" (I2C_SCLK and I2C_SDAT) but not sure.

[Altera_Forum]

If you have an oscilloscope, probe the HSMC connector pin and check that you can see a clock there. Alternatively, use SignalTapII - you don't have to use a synchronous clock for this, just use whatever clock is on the DE board to capture the clock pin from the HSMC board. If you do not see toggling, then you are not getting a clock with your data. 

 Read the data sheet to see what to do with the POWERON signal ... from its name I suspect you need to use it :) Probe the board and see if it is at the correct level to enable the ADC channel.  Cheers, Dave

[Altera_Forum]

Hi, thanks for your valuable suggestion.  

Now, I got the ADC output. I can see the output in Signal Tap analyser for individually 14 bits and also as a whole for all 14 bits in the hex form. For clarification, I attached the file here. even output also see on the led using counter.  using "create signal Tap II list file", I have also created one text file. but unfortunately this file is only for 128 samples (from -16 to +111) and unable to ctreate such file for more samples.  Is it possible to create such file for lets say thousands of samples??  Is it also possible to capture single waveform(not just as hex format) instead of individual 14 bits, same like analog signal so that further processing will be easy??.

[Altera_Forum]

--- Quote Start ---   Now, I got the ADC output. I can see the output in Signal Tap analyser for individually 14 bits and also as a whole for all 14 bits in the hex form. For clarification, I attached the file here. even output also see on the led using counter.   --- Quote End ---  Great! It looks like all bits are toggling.    --- Quote Start ---   using "create signal Tap II list file", I have also created one text file. but unfortunately this file is only for 128 samples (from -16 to +111) and unable to ctreate such file for more samples.  Is it possible to create such file for lets say thousands of samples??   --- Quote End ---  If you click on the Setup tab in SignalTap II, on the right is the sample depth. You can select the number of samples to capture there.    --- Quote Start ---   Is it also possible to capture single waveform(not just as hex format) instead of individual 14 bits, same like analog signal so that further processing will be easy??.  --- Quote End ---  I believe the data captured by SignalTap II can be read using external tools. However, I've never had to use that feature.  When I want to capture a block of samples from an ADC, I'll typically write my own code to capture to a RAM block or multiple RAM blocks. The RAMs are configured as dual-ported, with one side connected to the ADC, and the other connected to an Avalon-MM system. I then read the captured samples from RAM using the JTAG interface, via the method described in this tutorial  http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial  Cheers, Dave

[Altera_Forum]

Hi, As output from 14 bit ADC is in 2's complement form having 1 volt reference voltage. and I am trying to convert it into Sign Magnitude in following way: 

 process (CLOCK_50) begin  if rising_edge(CLOCK_50) then  if (ADC_DA(13)='1') then --for -ve value  calculation<=ADC_DA-1;  calculation<=NOT(calculation);  calculation(13)<= '1';  LEDR <= calculation;  else  LEDR<=ADC_DA; --for +ve value  end if;  end if;  end process;  but not getting desired output in signal tap anyser for LEDR here. Am I missing something??