A FIR FILTER , I cant understand

[Altera_Forum]

hi everyone: 

I just read a part of vhdl code . The code is used to do filtering. The data avSigCreg(9) which is summed will be taken into a digital filter. The code is shown below: ------------------- FIR FILTER ------------------  process(CLK80) begin if (CLK80'event and CLK80='1') then if (DFTrigCReg='1') then-- the avSigCreg(9) which is a sum of 10 datas will change now. for I in 0 to firLength-1 loop CQRealReg(I) <= avSigCReg(9)(17 downto 4) * DFcoeff(I);-- this looks like (avSigCreg/16)* DFcoeff end loop;  CSRealReg(0) <= CQRealReg(0)(23) & CQRealReg(0)(21 downto 0);  for I in 1 to firLength-1 loop CSRealReg(I) <= CSRealReg(I-1) + (CQRealReg(I)(23) & CQRealReg(I)(21 downto 0)); end loop; end if; --  end if; -- CLK end process; I think the DFcoeff is filter coefficient. But why the designer do the process like this" CSRealReg(0) <= CQRealReg(0)(23) & CQRealReg(0)(21 downto 0);" Thanks for your reading

[Altera_Forum]

Sign extension. Keping the value +Ve or -ve.

[Altera_Forum]

Thanks tricky 

CSRealReg(0) <= CQRealReg(0)(23) & CQRealReg(0)(21 downto 0). I think the designer ignored the CQRealReg(0)(22) . This process is used to sign extension?

[Altera_Forum]

Without knowing the data types of all involved signals, this isn't but guessing. 

 The bad of posting incomplete code snippets.

[Altera_Forum]

It could be, but like FvM said without the whole code its impossible to say. But this style can cause bugs if vectors are extended later and this code left unmodified. the resize function would always keep the correct sign.

[Altera_Forum]

--- Quote Start ---  It could be, but like FvM said without the whole code its impossible to say. But this style can cause bugs if vectors are extended later and this code left unmodified. the resize function would always keep the correct sign.  --- Quote End ---    The code is multiplying same data?? by all coeffs then summing up products. I don't know what this means in DSP sense.  It is discarding MSB bit(22) from each product. If you are sure this bit is never used then you might as well use it instead of bit 23 i.e. use (22 down 0) directly.  @tricky, I don't know if resize can remove a specific msb you target. This case is msb discarding andkeeping sign bit rather than sign extension.

[Altera_Forum]

--- Quote Start ---  The code is multiplying same data?? by all coeffs then summing up products. I don't know what this means in DSP sense.  --- Quote End ---   It doesn't seem to make sense in VHDL sense. Each CQRealReg(I) is assigned twice per clock cycle, so the first assignment is discarded. It seems like the design output doesn't depend on the input and all logic will be removed during synthesis.  The code is using VHDL signals as if they where variables.  Update: I overlooked that CqRealReg and CsRealReg are different signals. So the code is probably correct. But hard to read nevertheless. As previously mentioned by others, there are better ways to write sign extension etc. in VHDL.

[Altera_Forum]

--- Quote Start ---  The code is multiplying same data?? by all coeffs then summing up products. I don't know what this means in DSP sense.  It is discarding MSB bit(22) from each product. If you are sure this bit is never used then you might as well use it instead of bit 23 i.e. use (22 down 0) directly.  @tricky, I don't know if resize can remove a specific msb you target. This case is msb discarding andkeeping sign bit rather than sign extension.  --- Quote End ---   Thanks kaz, I think you're right.But I feel confused why the designer don't directly use the varaible CSRealReg(Its length is 0 to 22) instead of using a intermediate varaible(its length is 0 to 23) . I will show the integrity code as a attachment. It is a reciver for data acquistion .

[Altera_Forum]

Thanks FvM. I have shown the complete code in a attchment. If you're interesting about it , I'm happy to discuss with you . Actually it's difficult for me to understand it.