A one bit in vector is not assigned when assigment is out of the process

TSvob · ‎05-22-2020

    CheckOnes_P: process(gray_vector, no_ones_below)
    begin
            for i in 1 to WIDTH_C loop
                no_ones_below(i) <= no_ones_below(i-1) and not gray_vector(i-1);
            end loop;
    no_ones_below(0) <= '1';
    end process;

Bit 0 of no_ones_below vector is not assigned in simulation when this line is written out of the process. Why?

RichardTanSY_Altera · ‎05-27-2020

VHDL uses a process to model signal assignments that are based on an event and the signal assignments do not take place until the process ends.

TSvob · ‎06-02-2020

Sure, I know it, but assigment can be also done outside the proces. Note, that line 8 is placed outside the process - it will cuase (in simulation) that bit 0 is not assigned (it get U value)

    CheckOnes_P: process(gray_vector, no_ones_below)
    begin
            for i in 1 to WIDTH_C loop
                no_ones_below(i) <= no_ones_below(i-1) and not gray_vector(i-1);
            end loop;
  ---  no_ones_below(0) <= '1';
    end process;
   no_ones_below(0) <= '1';

RichardTanSY_Altera · ‎06-18-2020

Please help to share your design files and testbench so I can look into the simulation behaviour.