In my Quartus project,the clk of the ddio and dc_fifo is the same qds_bus_out.But the dqs_bus_out for the dc_fifo go through a clk_ctrl.So the data and clk between the ddio and the dc_fifo have 7ns delay.In the signaltap,the data and q of the fifo is different.But there is no problem in the Timequest.I can't find where the problem is! If the delay is the 4ns,the data and q of the fifo is same.
