accessing internal nodes

[Altera_Forum]

In verilog, I am trying to connect to internal nodes from the top level of a design for debug. The debug module is a serial input DAC control module that is used to look at internal nodes using an oscilloscope. It would be very painful to bring all the nodes I would like to look up through the hierarchy to a single location. I have simulated something similar with cadence ncsim before without an issue… I do believe the internal node needed to be a wire. Is there a way to do this in Quartus?  

 This is in the top module: hierTest    sysLogic I1 (  .IN(DATA[7:0]),  .CLK(CLK),  .RESET(RESET));      dacCtl I2 (  .IN(I1.I2.OUT[7:0]), // I1.I1.OUT[7:0] is the output a registers in I1.I1, Also tried a wire  .LD(I1.I2.LD),   .SDO(SDO)  .SCK(SCK),  .SLD(SLD),  .CLK(CLK),  .RESET(RESET));     Error (10207): Verilog HDL error at hierTest.v(31): can't resolve reference to object "OUT"   

[Altera_Forum]

--- Quote Start ---  In verilog, I am trying to connect to internal nodes from the top level of a design for debug. The debug module is a serial input DAC control module that is used to look at internal nodes using an oscilloscope. It would be very painful to bring all the nodes I would like to look up through the hierarchy to a single location. I have simulated something similar with cadence ncsim before without an issue… I do believe the internal node needed to be a wire. Is there a way to do this in Quartus?    This is in the top module: hierTest    sysLogic I1 (  .IN(DATA[7:0]),  .CLK(CLK),  .RESET(RESET));      dacCtl I2 (  .IN(I1.I2.OUT[7:0]), // I1.I1.OUT[7:0] is the output a registers in I1.I1, Also tried a wire  .LD(I1.I2.LD),   .SDO(SDO)  .SCK(SCK),  .SLD(SLD),  .CLK(CLK),  .RESET(RESET));     Error (10207): Verilog HDL error at hierTest.v(31): can't resolve reference to object "OUT"      --- Quote End ---     Hi,  why don't you use Signaltap ?  Kind regards  GPK

[Altera_Forum]

I need to see the internal signals in relation to other analog external signals. I don't know of a way to do this with Signal tap. I don't have an extra external DAC to bring the signals into the FPGA.  

  I did find out that Quartus doesn't support hierarchical names out side the current module. Not sure what referencing a hierarchical name inside the current module would be. Doesn't sound like hierarchy to me.     I started updating my code with `ifdef & `endif to route the signals up at compile time. What a mess.     I did see there is a tcl command called make_ape_connection that belongs to the chip_planner. I was thinking I could instantiate the modules an then hook the connections up with this this command. Has anyone done something like this?   Thanks, Lindy

[Altera_Forum]

--- Quote Start ---  I need to see the internal signals in relation to other analog external signals. I don't know of a way to do this with Signal tap. I don't have an extra external DAC to bring the signals into the FPGA.    I did find out that Quartus doesn't support hierarchical names out side the current module. Not sure what referencing a hierarchical name inside the current module would be. Doesn't sound like hierarchy to me.     I started updating my code with `ifdef & `endif to route the signals up at compile time. What a mess.     I did see there is a tcl command called make_ape_connection that belongs to the chip_planner. I was thinking I could instantiate the modules an then hook the connections up with this this command. Has anyone done something like this?   Thanks, Lindy  --- Quote End ---    Hi Lindy,  if you need the signals at device pins you can try the feature "Signalprobe". It is similar to Signaltap, but it routed the selected signals to device pins.  Kind regards  GPK

[Altera_Forum]

you'll have to route internal signals to actual pins for the fitter. 

 You can do this via the assignments editor. Add a new entry, right click in the "to" box and click on node finder. You should be able to find singals in a similar way you'd find them in signal tap - then you can assign them to a pin. It might not let you do that though - and the only way I can think of would be to route the signal to the top level in the source code .

[Altera_Forum]

I need to see the internal signals in relation to other analog external signals. I don't know of a way to do this with Signal tap. I don't have an extra external DAC to bring the signals into the FPGA.  

  I did find out that Quartus doesn't support hierarchical names out side the current module. Not sure what referencing a hierarchical name inside the current module would be. Doesn't sound like hierarchy to me.     I started updating my code with `ifdef & `endif to route the signals up at compile time. What a mess.     I did see there is a tcl command called make_ape_connection that belongs to the chip_planner. I was thinking I could instantiate the modules an then hook the connections up with this this command. Has anyone done something like this?   Thanks, Lindy

[Altera_Forum]

--- Quote Start ---  I need to see the internal signals in relation to other analog external signals. I don't know of a way to do this with Signal tap. I don't have an extra external DAC to bring the signals into the FPGA.    I did find out that Quartus doesn't support hierarchical names out side the current module. Not sure what referencing a hierarchical name inside the current module would be. Doesn't sound like hierarchy to me.     I started updating my code with `ifdef & `endif to route the signals up at compile time. What a mess.     I did see there is a tcl command called make_ape_connection that belongs to the chip_planner. I was thinking I could instantiate the modules an then hook the connections up with this this command. Has anyone done something like this?   Thanks, Lindy  --- Quote End ---    Hi Lindy,  did you give signalprobe a try ? Is it not usable for you ?  Kind regards  GPK

[Altera_Forum]

Hi GPK 

I looked into signal probe, but didn't have too much luck. It seems the destination wants to be a pin, and I need it to be a port to another module. I need to connect to a module that serializes the data for the external DAC.      Tricky...I'll give the assignment editor a try, maybe some type of ECO.      I wounder how Altera does it with the SignalTap II Logic analyzer?      Thanks for you help,  Lindy

[Altera_Forum]

--- Quote Start ---  Hi GPK  I looked into signal probe, but didn't have too much luck. It seems the destination wants to be a pin, and I need it to be a port to another module. I need to connect to a module that serializes the data for the external DAC.      Tricky...I'll give the assignment editor a try, maybe some type of ECO.      I wounder how Altera does it with the SignalTap II Logic analyzer?      Thanks for you help,  Lindy  --- Quote End ---    Hi Lindy,  I think I misundertand you. I though that you would like to see the internal signal directly on device pins, in order to measure the signals with e.g. a scope. It seems to me that you want to connect an additional block to internal signals of your design and the block is on the toplevel , right ?   Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Not sure what referencing a hierarchical name inside the current module would be. Doesn't sound like hierarchy to me.  --- Quote End ---   In deed. I found, that you're allowed to prefix a module internal item with it's module name without causing a syntax error. But it's of course meaningless.    --- Quote Start ---  I wonder how Altera does it with the SignalTap II Logic analyzer?   --- Quote End ---   Hierarchical names exist of course inside the design (in a AHDL or whatever syntax), but you don't necessarily have a high level (VHDL/Verilog) interface. Finding the exact internal item name can be even less comfortable then routing the signal through the hierarchies, I fear. You also have these problems in SignaTap II: A signal, that appears in the node browser is not necessarily accessible in the same module.  Supporting the well-defined hierarchical names mechanism of Verilog (my favourite VHDL unfortunately hasn't it) would be an actual high level approach. In VHDL, I have the option to use a structured inout signal as a debug "bus", that can be connected where needed. It possibly works with a bit vector in Verilog as well.

[Altera_Forum]

GPK, 

Yes I want to connect some internal logic that controls an external serial DAC. I just want to connect the input to this module to other circuit nodes without writing/rearranging my verilog code.  Regards, Lindy

[Altera_Forum]

FvM, 

That's a good idea. I think if I was starting my design from scratch, I would add the hook in the port list for a debug bus and maybe a compiler directive to switch it in & out. Maybe using a tri-state assignment and letting the compiler convert it to muxs. I know this conversion works in a single module, but I never tried it connecting separate modules.  Regards, Lindy

[Altera_Forum]

In VHDL, it's sufficient to initialize the port to (others =>'Z') to disable all drivers to the bus by default. If no drivers exist, the bus will effectively discarded in synthesis. Muxes will be generated, if specific bits have multiple drivers and are selected by a global select signal.

[Altera_Forum]

--- Quote Start ---  GPK,  Yes I want to connect some internal logic that controls an external serial DAC. I just want to connect the input to this module to other circuit nodes without writing/rearranging my verilog code.  Regards, Lindy  --- Quote End ---     Hi Lindy,  I don't think there is a feature in Quartus which solve your problem. How many signals do you need ? Will they change during the project ?  Kind regards  GPK

[Altera_Forum]

Hi GPK, 

Currently I have 5 different signals, but this can change. Just like the logic analyzer.   Lindy