A shift register question ?

Altera_Forum · ‎07-19-2011

Hi, I am required to write the VHDL code for a 4-bit shift register with active-high clock and asynchronous preset. Below is the architecture declaration.

architecture operation of shiftreg is
	signal regs : std_logic_vector((n-1) downto 0); -- note: n = 4
begin
	process(PRESET, CLK)
		begin
			if (PRESET = '1') then
				regs <= (others => '1');
			elsif (CLK = '1' and CLK' event) then
				regs <= regs((n-2) downto 0) & SI;
			end if;
	end process;
	PO <= regs;
end architecture operation;

Check the .jpg file that I attached. Anybody can explain why the PO output is HIGH even though the input is LOW at the beginning? Thank you in advance.

*edit*

Never mind, I figured out why, thanks for looking.

Altera_Forum · ‎07-19-2011

In the picture you posted, N is clearly 4, not 2.

Altera_Forum · ‎07-19-2011

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In the picture you posted, N is clearly 4, not 2.

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Hi, it was my mistake, n is supposed to be 4 and not 2.

Altera_Forum · ‎07-19-2011

I don't hear a clear question. Initially, all outputs are high. P(0) changes to low on the first clock edge. It may be the case, that you didn't think about output delays. This is a timing analysis, however, and 200 MHz clock is pretty fast.

Altera_Forum · ‎08-18-2011

Your implementation produces quite a different output from the book's. You should prove this to yourself by constructing a simple testbench to drive your inputs and run a simulation.

Altera_Forum · ‎08-18-2011

Answering the question:

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Check the .jpg file that I attached. Anybody can explain why the PO output is HIGH even though the input is LOW at the beginning? Thank you in advance.

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You very probably compiled the project with the 'Power-Up Don't Care' box in the Assignments->Settings->Analysis & Synthesis Settings section checked (as it is by default). As you have a preset in your code the compiler has extended this for the power-up as well. You can un-check that box and see what happens next ...