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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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ALTASMI_PARALLEL in full synchro design. Can I use the same clock and edge (rising edge ) for clkin and the rest of the design?

NJOUB1
Beginner
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a_x_h_75
New Contributor III
149 Views

Yes.

Cheers,

Alex

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