I m trying to implement an 600Mbps Arbitrary Waveform Generator as my postgraduate project. I want to write data from a SRAM memory that uses CMOS interface to a DAC that uses LVDS Interface. I also need to use some kind of buffer/multiplexer that receives 48 bits at 150 Mhz from the SRAM and feeds the DAC with 12 bits at 600 MHz. This is because my SRAM runs at 200 MHZ maximum and because I cant use a deserialization factor of 3. In order to achieve this, I used the ALTLVDS Megafunction transmitter. The number of LVDS channels is 12, the deserialization factor is 4, I use an internal PLL, the output Data Rate is 600 Mbps and I feed the FPGA with an 20Mhz Oscillator as a clock reference. My problem is, that when I create the block diagram at Quartus and then try to simulate it using VWF, the Waveform makes no sense to me at all. I know that there are different kind of SERDES architectures such as Parallel Clock, Embedded Clock, 8b/10b or Bit Interleaving, but what I come up with after simulation ends, doesn't look like any of them. Isn't the Megafunction supposed to work as a Multiplexer where, for example, Input CMOS channels 0-3 fed in parallel and at low data rate to the Megafunction would be buffered to drive the first (0) LVDS output channel in serial at a high data rate? Is the SERDES architecture more complicated than this or am I doing something wrong?
Thanx
