Quartus Fitter messages

[Altera_Forum]

I get the following fitter message from quartusII 7.1 

 Info: Ignoring invalid fast I/O register assignments   But there is no further information. How can I get the information which register assignment is ignored. In my design there are over 200 Fast I/O register assignments, I don't want to check every assignment.   Thanks for help   okar

[Altera_Forum]

Usually those info messages can be expanded to show which one was ignored. If it doesn't, open the Compilation report, go to Fitter -> Resource Section and in there are a table on Inputs, Outputs and Bidirs. It should have a column if the register is used. Not ideal since some of them you don't want, but it should work. 

Note that I recommend against using this assignment. If you use timing constraints to constrain your design, the fitter will use I/O registers when need be. (If it can still meet I/O requirements but move the register internal to help internal timing it will. Plus, the I/O elements have delay chains, so technically you could use an I/O register but have bad timing because of the delay chain(although this won't happen)). Most importantly, it's strongly recommended to do timing constraints on I/O regardless.

[Altera_Forum]

Not very comfortable but it works, thanks. 

 I make timing constraints too, thanks for your recommendation.   regards

[Altera_Forum]

If your constraints are correct, then static timing analysis will tell you if you made timing, and whether an I/O register is used is irrelevant. It can take getting used to, but I see this method on most designs. 

(As an aside, there was an architecture put out many, many years ago that didn't have an I/O register, but had a really fast connection between the LAB registers and the I/O. From a timing perspective there really wasn't much difference, but a number of people were very unhappy, whether it met their requirements or not...)

[Altera_Forum]

--- Quote Start ---  Note that I recommend against using this assignment. If you use timing constraints to constrain your design, the fitter will use I/O registers when need be.  --- Quote End ---    Interesting, can you elaborate a bit more. I realize the trade-off with internal timing, but I use to force fast I/O, at least in two cases.  One is when using fast async devices, such as ASYNC SRAM. That was a PITA to constraint, at least until recently. I understand that Quartus 9 supports data skew constraints that might help here, but I didn't try that yet.  The second case is when using a PLL phase shift, such as with SDRAM. You need to know the internal delays before computing the ideal phase shift. And you can't reliably do that without fast I/O. I agree that if you constraint and meet timing, then in theory you are ok, even when the fitter decided to not use fast I/O. But this might mean the phase shift is not optimized, giving you a smaller I/O timing slack.

[Altera_Forum]

--- Quote Start ---  I get the following fitter message from quartusII 7.1   Info: Ignoring invalid fast I/O register assignments. But there is no further information.   --- Quote End ---    I think that some (most) versions of the fitter always give that message.  If some fast I/O assignment were actually ignored, then further details are provided at the warning message level. If there are no warnings, then no assignment was ignored.  Seems a fitter buglet. Possibly the intent was to put something like "Checking for invalid fast I/O assignments".

[Altera_Forum]

ASYNC SRAM is probably a good place, as you're right, it's a PITA to constrain. (In reality, just guardbanding it with constraints is usually fine, just something that works. If you had really tight timing, then you probably would want to spend the time to get them right...)