I'm using cyclone 10 lp which is 10CL120YF484I7G on my own board.
My problem is when I made clock using alt pll, the clock's phasee didn't matches.
Actually, I'm using 2 alt pll to make some clocks. is it problem?
why the clocks does not synchronize?
I set normal mode in alt pll and others are default.
Input clock is 32Mhz, outputs 12.288Mhz, 3.072Mhz, 48KHz.
I attached a capture which is part of clocks
please give me some details.
Thanks for your inquiry. May I know if your input reference clock is misaligned with PLL's output clock? Or do you mean you have multiple PLL's outclocks misaligned?
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