ALTPLL synthesis issue

[Altera_Forum]

I am trying to use ALTPLL megafunction in my design. I generated the IP using the megafunction IP manager. then i've instantated that in my top-level design and hooked it up in the following manner. 

 module designTop (  inclk0, PLL_RESET, PLL_LOCKED, SYSCLK, CR4CLK );  input inclk0, PLL_RESET;  output PLL_LOCKED, SYSCLK, CR4CLK;    pcst_sysclkpll pcst_sysclkpll_inst (  .areset ( PLL_RESET ),  .inclk0 ( inclk0 ),  .c0 ( SYSCLK ),  .c1 ( CR4CLK ),  .locked ( PLL_LOCKED )  );  endmodule   I get the following error:   Info: Input port INCLK[0] of node "pcst_sysclkpll:pcst_sysclkpll_inst|altpll:altpll_component|pcst_sysclkpll_altpll:auto_generated|pll1" is driven by inclk0~buf0 which is COMBOUT output port of LOGIC_CELL_COMB type node inclk0~buf0   Error: Clock input port inclk[0] of PLL "pcst_sysclkpll:pcst_sysclkpll_inst|altpll:altpll_component|pcst_sysclkpll_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block   Even though i've connected the inclk0 to a top-level input pin, Quartus is placing a buffer before the inclk0 pin of the PLL resulting the above error. how do i resolve this? Thanks

[Altera_Forum]

What device are you using and which pin is inclk0 assigned to?

[Altera_Forum]

Iam using startixIII EP3SL340F1517C3. i've assigned it to pin_AA1 which is a dedicated CLK pin (CLK8n) and IOBank_5C. 

Thanks.

[Altera_Forum]

Hi, 

I have just replicated your design and PLL including pin placement and do not have the error that you observed.  What version of Quartus are you running?  Rgds V

[Altera_Forum]

i am using vesion 8.0 SP1, build 07/10/2008 SJ Full version. 

 I have tried the following things in my end and still have the issue: A. Assigning pin location thru synthesis directive instead of thru pin planner:  input inclk0 /* synthesis chip_pin = "AA1" */; // input Clock I got the same error.   B. Driving the PLL input thru altclkctrl in the following manner:  altclkctra pcst_altclkctrl_inst1 (  .inclk (inclk0),  .outclk (pll_clkin) );  pcst_sysclkpll pcst_sysclkpll_inst (  .areset ( PLL_RESET ),  .inclk0 ( pll_clkin ),  .c0 ( SYSCLK ),  .c1 ( CR4CLK ),  .locked ( PLL_LOCKED )  );   I got the following error: Error: Clock input port inclk[0] of PLL "pcst_sysclkpll:pcst_sysclkpll_inst|altpll:altpll_component|pcst_sysclkpll_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block  Info: Input port INCLK[0] of node "pcst_sysclkpll:pcst_sysclkpll_inst|altpll:altpll_component|pcst_sysclkpll_altpll:auto_generated|pll1" is driven by altclkctra:pcst_altclkctrl_inst1|altclkctra_altclkctrl_nie:altclkctra_altclkctrl_nie_component|wire_clkctrl1_outclk which is OUTCLK output port of CLKCTRL type node altclkctra:pcst_altclkctrl_inst1|altclkctra_altclkctrl_nie:altclkctra_altclkctrl_nie_component|clkctrl1   eventhough it is driven by CLKCTRL node, i get the same error and dont understand why.

[Altera_Forum]

--- Quote Start ---  i am using vesion 8.0 SP1, build 07/10/2008 SJ Full version.   I have tried the following things in my end and still have the issue: A. Assigning pin location thru synthesis directive instead of thru pin planner:  input inclk0 /* synthesis chip_pin = "AA1" */; // input Clock I got the same error.   B. Driving the PLL input thru altclkctrl in the following manner:  altclkctra pcst_altclkctrl_inst1 (  .inclk (inclk0),  .outclk (pll_clkin) );  pcst_sysclkpll pcst_sysclkpll_inst (  .areset ( PLL_RESET ),  .inclk0 ( pll_clkin ),  .c0 ( SYSCLK ),  .c1 ( CR4CLK ),  .locked ( PLL_LOCKED )  );   I got the following error: Error: Clock input port inclk[0] of PLL "pcst_sysclkpll:pcst_sysclkpll_inst|altpll:altpll_component|pcst_sysclkpll_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block  Info: Input port INCLK[0] of node "pcst_sysclkpll:pcst_sysclkpll_inst|altpll:altpll_component|pcst_sysclkpll_altpll:auto_generated|pll1" is driven by altclkctra:pcst_altclkctrl_inst1|altclkctra_altclkctrl_nie:altclkctra_altclkctrl_nie_component|wire_clkctrl1_outclk which is OUTCLK output port of CLKCTRL type node altclkctra:pcst_altclkctrl_inst1|altclkctra_altclkctrl_nie:altclkctra_altclkctrl_nie_component|clkctrl1   eventhough it is driven by CLKCTRL node, i get the same error and dont understand why.  --- Quote End ---    Hi,  I run your code with Quartus II 8.0 SP1 (Full Version) ,including the pin assignment for the input clock, and it works fine. Did also constrain the other pins ?

[Altera_Forum]

After i deleted all my pin assignments and ran, i didn't get the error. didn't understand why my assignments was causing the above error. But now it is resolved. Thanks everyone for the timely tips.