If you're spending hours and hours trying to figure out why your DDR source synchronous (FPGA=transmitter) interface is not meeting hold time to your interface's generated clock, you might try the following QSF/TCL assignment:
set_global_assignment -name AUTO_DELAY_CHAINS OFF
Wonders may ensue.
It seems that the fitter's output pin delay algorithm is:
A. Increase delay through the clock buffer until setup time is ridiculously easy to meet
B. Forget that you added this monstrous delay when you can't meet hold time
