Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

About Clock Constraints

Yamada1
Beginner
746 Views

I want to apply a timing constraint, but when I create an SDC file and try to specify it with create clock or click the List button on the Name Finder, I get the error "Error: In order to edit SDC constraints, you must first run the Create Timing Netlist command in the Timing Analyzer to view the list of available nodes." and I cannot select a signal.

It was the same even if it was implemented with a design that had completed up to Timing Analysis.

Registering the SDC file to Quartus while it is empty and running create clock did not change the situation.

 

Any advice would be appreciated.

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IntelSupport
Community Manager
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You can just compile to have the timing netlist during (post map/post fit). In Timing Analysis, there should be able to detect the clock you specify in sdc. Also I suggest you to migrate to latest Quartus for better usability and there lot of bug/fix.


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sstrell
Honored Contributor III
734 Views

As the error states, you have to create a timing netlist to use those features.  This is separate from compiling the design.  The timing netlist is based on completed stages of compilation, either synthesis or fitting.  It's a database of timing information based on a stage of compilation and is required for working with the tool.

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Yamada1
Beginner
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Thank you for answering.

I understand that even if Start Compilation is completed up to Timing Analysis, a timing netlist will not be created.

I also checked here, but is the following procedure correct for creating a timing netlist?

1) Start Timing Analyzer

2) Netlist → Create Timing Netlist on the Timing Analyzer

At the stage up to synthesis, the above procedure will also fail with a message telling you to complete the fitting.

It would be helpful if you could also teach us the procedure for creating a timing netlist at the stage of completing synthesis.

I apologize for the inconvenience, but it would be helpful if you could teach me.

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sstrell
Honored Contributor III
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Are you using Standard (Lite) or Pro? If Pro, you have to have completed at least the Plan stage of the Fitter. In Standard you can create a post-synthesis timing netlist. This is not available in Pro.
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Yamada1
Beginner
701 Views

Thank you for answering.

The Quartus I am using is the Standard Edition.

The device used is Arria10 GX, and the version of Quartus is 18.1.1. For the time being, we will proceed with the design after the fitter is completed.

 

I apologize for the inconvenience, but it would be helpful if you could teach me.

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sstrell
Honored Contributor III
696 Views
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IntelSupport
Community Manager
662 Views

You can just compile to have the timing netlist during (post map/post fit). In Timing Analysis, there should be able to detect the clock you specify in sdc. Also I suggest you to migrate to latest Quartus for better usability and there lot of bug/fix.


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IntelSupport
Community Manager
626 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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