About DPRAM of IP created with Quartus

[mikami]

Quartus IP を使用して DPRAM を作成しましたが、RD/RW イネーブル信号はアクティブ High ですか、それともアクティブ Low ですか。

[Jeet14]

Hi,

The write enable (wren) signal is High, together with the byte enable (byteena) signal, control the write operations on the RAM blocks. By default, the byteena signal is high (enabled) and only the wren signal controls the writing.

Reference user guide- https://cdrdv2-public.intel.com/667041/ug_ram_rom-683240-667041.pdf

Regards

Tiwari

[Jeet14]

Hi,

Please let me know if you have any other query on this.

Regards

Tiwari

[Jeet14]

Hi,

As I do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Regards

Tiwari