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About VHDL description


After converting A/D conversion data to 2's complement value, I created float (IEEE754 32bit) conversion, but it does not work well.

Float conversion, 2's complement conversion, and peripheral part alone work, but when everything is connected, it doesn't work well.

As far as I have checked here, it does not appear to be a problem in terms of RTL, but it is possible that there is an "inappropriate description in terms of VHDL syntax that is not extracted by the compiler".

Sorry to trouble you, but it would be helpful if you could teach us the following points.

1) If the conditional expression part of the if statement is enclosed in parentheses, Is it okay if there is no space between if,then and parentheses?

2) Is there any problem with the following description in the description of the case statement?

  process(N_RST, AD_CLK)


      if (N_RST = '0') then

          s_connect_sig_buf <= (others => '0');

      elsif (AD_CLK'event and AD_CLK = '0') then

         case s_sig_cnt(3 downto 0) is

            when "0000" => s_connect_sig_buf(13 downto 0) <= AD_DATA_SIG;

            when "0001" => s_connect_sig_buf(27 downto 14) <= AD_DATA_SIG;

            when "0010" => s_connect_sig_buf(41 downto 28) <= AD_DATA_SIG;

            when "0011" => s_connect_sig_buf(55 downto 42) <= AD_DATA_SIG;

            when "0100" => s_connect_sig_buf(69 downto 56) <= AD_DATA_SIG;

            when others => s_connect_sig_buf <= (others => '0');

        end case;

      end if;

  end process;


3) There are places where TAB instead of space is used between the signal name and ":" in the Entity, signal statement.Is this a problem?

4) There is a place where TAB instead of space is used between the signal name and "<=" in the assignment statement.Is this a problem?

Any hints to solve the problem would be greatly appreciated.

Please note that the .vhd file itself is provided by another company and cannot be posted here.

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10 Replies
Honored Contributor III

You provide all this info...except what the actual problem is.  The code you have there looks fine.  What error or warning messages are you getting and what line numbers are they pointing to?  Provide that and the code that it's referring to.  Whitespace type does not matter.

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Thank you for answering.

There are some warnings in the compilation result.

As content

 Warning (13410)

 Warning (15610)

and for pins with fixed outputs or undriven input pins.

Should input pins that have no drive destination be commented out or output to a monitor, etc.?

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Valued Contributor I

Hi @Yamada1 ,

It's unclear from your message what specifically you mean by " it does not work well".

But, short answers to your specific questions, in order of simplicity:

1) Yes, that's ok as far as VHDL is concerned.  Whitespace around the parentheses is optional.

3) and 4)  Not a problem as far as VHDL is concerned.  It doesn't care about what type of whitespace characters you use.

2) The case statement itself looks ok, if the functionality is what you intended.  But your code snippet contains an oddity, the use of a negative edge clock.  Not something you'd want to do in general, unless you have a very good reason and a very good understanding of the issues involved in crossing between regions of logic using opposite edges of the clock.  Is this possibly what's biting you when interfacing with other modules?...  Also, you're using an asynchronous reset, which in most situations can and should be avoided, again, unless you have a good reason and good understanding of the issues involved.

And in general, I would encourage you to go gain at least some basic working proficiency in VHDL if you're going to be working with it.  You can't learn VHDL from a message board.  I recommend the books written by Peter Ashenden as a good starting point.




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Thank you for pointing out the details.


"it does not work well" means that the 2's complement to floating point conversion part does not work as intended.


Also, the negative edge clock is used because the FIFO is connected after this, and the FIFO user guide states that the data transitions with the negative edge clock. (FIFO uses IP)


Asynchronous reset part inputs power-on reset signal It is the part that is not driven by other logic in the FPGA while the FPGA is running.

I understand that asynchronous resets should be avoided unless there is a specific reason to do so.


Thank you for your patience in answering even my elementary questions.

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Honored Contributor III

Just paste the whole messages you are getting.  Just the message numbers does not help.

And you still haven't mentioned what is not working as you expect it to.

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Honored Contributor III

Well, without the code, there is not much more that can be done here.  You say you can't post it, so without knowing how you are trying to do the conversion that is not working as intended, I don't think you'll be able to get much more help.

Have you simulated the design?  Have you used an on-chip debugging tool like Signal Tap?  There's lots of other debugging you can perform on your own that maybe you could show us the results of that could help.

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Valued Contributor III
I don't recognize how the posted VHDL snippet is related to the mentioned problem of getting wrong data. Most likely the problem is in a different part of your design.
As suggested, simulating the design is a good way to trace the problem. Or post the complete data path VHDL.
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Valued Contributor I


We've all been trying to help you, but you've still not provided sufficient information for us to even guess at the nature of what may be going wrong with your design.  It's been all too vague and disjointed.

And I'm sorry to say but your responses regarding the clock and reset also don't give me the impression that you have a strong grasp of those issues.

All that aside, I will echo once more the key question raised by @sstrell and @FvM :  Have you verified your design in simulation?

Is your design failing to function as intended in simulation?  Or are you seeing a mismatch in how it's functioning in hardware vs. simulation?  Or, where and what exactly is it that you're seeing that's going wrong?

And, here and in general, if you've not performed functional verification of your design in simulation, then it's premature to even attempt to go down the hardware implementation flow before having done that.



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Hi Yamada,

Let me know if there is any update from previous reply?

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