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CycloneVsoc dev kit UART read from FPGA/HPS

CAlex
New Contributor II
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Hi,

My hardware is Cyclone V soc Dev kit with software of newest version of GHRD.

I encountered several questions on handling the UART. 

1. According to the GHRD QSYS HPS Mux Table:

CAlex_0-1684321396772.png

UART RX/TX was sent to CAN RX/TX

CAN RX/TX was sent to UART RX/TX

Is that mean my set to UART port (software wide) is linked to CAN(hardware wide,J35 CAN )

and my CAN port(software) is linked to UART (J8 with RX/TX option)?

If is that so, then auto_semihosting is always sending through CAN (software) with UART(J8 port)?

 

2. FPGA reading/sending through UART

How to let FPGA read/write through HPS UART? 

In the HPS design tab I can set the UART to FPGA, and get the export port, but how to use that port?

Another question would be : can hps use UART at the same time? Like when I was debugging through arm ds and then transfer the data to FPGA and let FPGA send the data to my host.

 

3. Let's say the answer of the 2nd question is NO, HPS and FPGA cant communicate with UART at the same time, then how do I manage the CAN port. I mean what's the data width of CAN port,where can I find the information etc.

 

4.How to send data to the on-chip-ram from HPS and let FPGA receive data from the OCRAM.

According to the GHRD:

CAlex_0-1684323994784.png

There is an 65536 bit on chip ram on FPGA side.

Is that the same ram used in HPS example Makefile(make memory = ocr)?

As I know the on-chip memory is 0xC000_0000 + RAM offset, but the OCR is 0xFFFF0000 right?

 

5. How to instore the codes in the ROM?

Now I'm debugging the bare metal projects with ARM DS, but I must download/boot the board every time, is there some methods to solve this problem?

 

That's it.

Looking forward to ur reply

 

Reguards

Alex

 

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8 Replies
JingyangTeh
Employee
1,296 Views

Hi Alex

 

1)

That is the Mux table.

The mux table shows the possible pins that the pins could be switched to.

 

In the GHRD the UART0 (Set 2) and CAN0 (Set 0) was selected.

From the MUX table they are different pins.

 

2)

There is a dedicated UART from the HPS.

I don't quite understand what you are trying to achieve here.

You could add a soft IP in the FPGA fabric and connect it to the HPS UART.

 

4)

Could you point me to the make file that you are referring to?

 

5)

There is a way you could place your baremetal code in teh QSPI flash and with the uboot. launch the baremetal application.

You could refer to the word document attached.

 

Regards

Jingyang, Teh

 

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CAlex
New Contributor II
1,283 Views

2. What I want to achieve is that I want to use HPS calculate and send the data to the on-chip ram IP and let FPGA read/write and then send them to the host through UART/CAN. Since I need to use UART(J8) as semihosting I can only use CAN.

4. On the baremetal example, each one of them will have a choice of MEMORY ?= DDR/OCR. If I choose OCR the entry point would be 0xFFFF0000 right?

 

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JingyangTeh
Employee
1,202 Views

Hi Alex


For transfering of data between the HPS and FPGA fabric. You could use a DMA to transfer data in between.

You could refer to the example here:

https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/fpga-to-hps-bridges-design-example.html


Yes, the entry point for on-chip ram is 0xFFFF0000.


Regards

Jingyang, Teh



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JingyangTeh
Employee
1,157 Views

Hi


Do you have any new updates for this case?


Regards

Jingyang, Teh


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CAlex
New Contributor II
1,132 Views

We bought a module to set the SPIM as the Uart, I now finished the host program to read that.

And the FPGA side I loan the HPS IO to the FPGA and they communicated with each other successfully.

But SOC(HPS) side there are two issues:

1. how to let HPS send the data to a RAM(an FPGA IP along with the GHRD).

2. how to let uart receive the data from that IP.

 

Reguards

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JingyangTeh
Employee
1,096 Views

Hi Alex


Is it possible that the HPS would send the data directly to the IP since the HPS has a copy of the data to be written into the RAM?

Could you elaborate what is a SPIM?


Regards

Jingyang, Teh


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CAlex
New Contributor II
1,066 Views

Hi,

it is shown on the first picture, it is SPIM0 MOSI and MISO.

I solved the problem , the loanIO need the preloader to init the system.

After the init it worked.

 

Reguards.

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JingyangTeh
Employee
1,031 Views

Hi


Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.


Regards

Jingyang, Teh


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