Hello,
I am currently working on a design that loads data to a DDR3 SDRAM via a NIOS processor. Now I want to access this data from the logic side (VHDL or Verilog).
I have read about using a MM-Pipeline Bridge, connecting the pipeline's master to the EMIF's amm_slave and exporting the pipeline's slave outside of Platform Designer/Qsys.
I have done that and to test the system very simply, I asserted the pipeline's slave read signal. This propagated through the pipeline's master read signal but I didn't see an assertion in the EMIF's amm_read. I am not sure why this is happening. Could you please advise.
I have tried running the logic on 133MHz the same as the EMIF's input clk, but the problem persists.
Is this the correct way of doing things?
Is there a better idea on how to obtain the SDRAM's stored values through logic?
My system:
Stratix 10 GX board
EMIF DDR3, DQ width of 72 (ECC is checked), running at a 1066MHz, Quarter rate, and supplied with a 133MHz clk.
