Add subtract seven segments display

Altera_Forum · ‎04-17-2016

I am going to pre-apologize for posting something so elementary on this site. I have taken a class where we have basically been told that Verilog is a programming language now go code a 7 segment display in ISE design suite. We have been taught absolutely nothing about Verilog so this is quite the frustrating endeavor for me.

The goal is to take two inputs A,B and an Overflow S and either subtract B from A if Overflow=0 or add the two if Overflow = 1. We are to then have the correct answer displayed on a 7 segment display. I have pasted what I have come up with so far below. Any help would be greatly appreciated. I am extremely lost.

module AddOrsubtractThenSelectAndDecodeInto7SegmentDisplay(

input [3:0] A,

input [3:0] B,

input [1:0] S,

output [3:0] Output,

output reg [1:0] Overflow,

output reg [6:0] Display

);

reg [3:0] Output_reg;

wire [3:0] A;

wire [3:0] B;

wire [1:0] S;

always @(S or A or B)

begin:Ouput_reg

if (S == 1'b1) begin

Output_reg = A + B;

end else begin

Output_reg = A - B;

end

endmodule

module Seven_dig(

Overflow,

Output_reg,

Display

);

input Overflow,Output_reg;

output Display;

reg Display;

always @({Overflow,Output_reg}) begin

case ({Overflow,Output_reg} )

5'b00000: Display = 7'b1111110;

5'b00001: Display = 7'b0110000;

5'b00010: Display = 7'b1101101;

5'b00011: Display = 7'b1111001;

5'b00100: Display = 7'b0110011;

5'b00101: Display = 7'b1011011;

5'b00110: Display = 7'b1011111;

5'b00111: Display = 7'b1110000;

5'b01000: Display = 7'b1111111;

5'b01001: Display = 7'b1111011;

5'b01010: Display = 7'b1110111;

5'b01011: Display = 7'b0011111;

5'b01100: Display = 7'b1001110;

5'b01101: Display = 7'b0111101;

5'b01110: Display = 7'b1001111;

5'b01111: Display = 7'b1000111;

5'b00000: Display = 7'b1111110;

5'b10000: Display = 7'b1111110;

5'b10001: Display = 7'b0110000;

5'b10010: Display = 7'b1101101;

5'b10011: Display = 7'b1111001;

5'b10100: Display = 7'b0110011;

5'b10101: Display = 7'b1011011;

5'b10110: Display = 7'b1011111;

5'b10111: Display = 7'b1110000;

5'b11000: Display = 7'b1111111;

5'b11001: Display = 7'b1111011;

5'b11010: Display = 7'b1110111;

5'b11011: Display = 7'b0011111;

5'b11100: Display = 7'b1001110;

5'b11101: Display = 7'b0111101;

5'b11110: Display = 7'b1001111;

5'b11111: Display = 7'b1000111;

default: Display = 7'b0001111;

endcase

end

endmodule

Altera_Forum · ‎04-18-2016

Hi

Dont worry - no question or code is too basic, we all had to start somewhere.

First off - I hope you werent told that Verilog is a programming language - it is nothing of the sort - it is a hardware description language. Thinking of it as a programming langauge will cause you problems.

Seconly, ISE is a Xilinx software suite and this is an Altera forum. While people can help with the HDL, they are unlikely to know much about how to use ISE. I suggest the Xilinx forum instead for these questions.

thirdly, you havent actually posted what problems you are having. Just posting the code and asking for help without specific questions is unlikely to receive a response.

So my questions : have you written a testbench? have you tried simulating your code?