Multiple state machines in one module

[Altera_Forum]

How do I create multiple state machines in the same module (but different always blocks), and have them recognized as state machines by Quartus II? I used the method recommended in an Altera handbook for creating a state machines using "state" and "next_state" for one state machine, then I used "state_x" and "next_state_x" for the second state machine. When I ran the analysis & synthesis, then went to the state machine viewer, it only showed my first state machine. If I commented out the first state machine, and changed the second state machine's reg names to just "state" and "next_state" and re-ran the analysis & synthesis, then that state machine would show up. So, I know each state machine is written properly, but Quartus II is only recognizing one state machine at a time. I want Quartus to recognize each state machine because the documentation says Quartus is then able to optimize those state machines. So how do I get Quartus II to recognize more than one state machine in one module?

[Altera_Forum]

Just add more than one state machine. 

 Quartus seems to recognise any case statement which changes a register between different entries as a state machine. I call all my state machines things like "stateMachine", "mgmtStateMachine", etc.  It helps to use (in Verilog at least) localparam definitions for each of your states.

[Altera_Forum]

--- Quote Start ---  Just add more than one state machine.  Quartus seems to recognise any case statement which changes a register between different entries as a state machine. I call all my state machines things like "stateMachine", "mgmtStateMachine", etc.  It helps to use (in Verilog at least) localparam definitions for each of your states.  --- Quote End ---    I found that unless each state machine follows very specific rules, they won't show up. It is also possible that you're missing something, for example using a blocking assignment instead of a non-blocking in a single state, that is causing issues. Getting the syntax correct can cause a headache for the viewer. I'd double-check that first.  I have several modules with 3+ state machines, so it has to be something else. I write mine differently (all synchronous), but it works either way.