Verilog Question with Quartus.

[Altera_Forum]

I use verilog in my Quartus designs and like using the "parameter" statements. When I design a new module and use the statements everything works fine. My problem is when I change the value of the "parameter" it always keeps the last value I assigned. 

 If there a "Clean" compile or something like that I could do to get the new value to be recognized?  Thanks in advance for the help! Brandon

[Altera_Forum]

Are you setting parameter values through Quartus or in your source code? I'm guessing Quartus since I can't imagine a source file change not being seen. When you set parameters through Quartus they will end up in your .qsf file. If that's what's going on then after you change the value, check your .qsf file and see if the change is reflected. Maybe you need to push the "Apply" button after making the change? And after changing the value you'll have to re-synthesize for it to take effect. 

 By the way, you can "clean" you project under the Project menu: Project -> Clean Project ...

[Altera_Forum]

Thank-you for your reply!! 

I'm using the "parameter" statement in the verilog source file not through Quartus. I am using an older version of Quartus which is version 9.1. (last time we licensed it) I wonder if this could be a problem in this old version. Also I don't see a "clean" under the project menu. Could this also be a feature in newer versions of Quartus? (Maybe I'm just blind) I'm not familiar with what files can be deleted before compiling (like C object files) that might fix the problem.  Any help would be greatly appreciated! Brandon

[Altera_Forum]

Hi Brandon - 

 That's an old version and I don't remember what has changed since then. Maybe someone else will chime in on that. As to what files you can delete, basically everything except the .qfp, .qsf and .sdc files. And your source files and IP core files of course. Everything else you can nuke, including the db folder that Quartus creates in your output file directory.  Very strange that the parameter change in your source file is not being seen. Are you sure that synthesis is finishing successfully and that you're not looking at old output files from a prior build? Make sure you're not getting any warning or error messages about programming files not being generated due to a licensing problem or anything else. And check the time/date of the .sof file to make sure it matches the time of your latest compile.  That's about all I can offer. If you can't resolve this the next step is probably to open a service request.  Good luck. Bob

[Altera_Forum]

Bob, 

 Thanks a ton for all your help! I will give your suggestions a try!  Have a good day, Brandon

[Altera_Forum]

I had a similar problem when I converted a Verilog module to a symbol for use on a schematic. Changes to the parameter file were not updated in the symbols. Are you using symbols?