Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17266 Discussions

Adjustment of clock phase shift in source synchronous outputs

Altera_Forum
Honored Contributor II
‎07-29-2011 10:01 AM
1,684 Views

Hi, 

simple question: is it possible to get Quartus to automatically adjust the phase shift of a clock at fitting time to meet required skew requirements on a source synchronous output bus? 

 

I find that I have to constantly tweak the PLL megafunction to adjust the output clock phase shift until I can meet my timing. It would be nice if the fitter had some control over this. It's a pain since my test build and my full build require different phase shifts to account for differing delays in other unrelated logic. 

Thanks,
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎07-29-2011 02:58 PM
947 Views

Unfortunately, it is not currently possible to do that. Altera Software is aware that this is something users would like to do, but it has not been a priority for them up to this point. Hopefully we will see that feature at some point in the future. For now, you have to manually change the clock phase.

0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎07-29-2011 03:51 PM
947 Views

OK that's fine.  

Many thanks,
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.