Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17255 Discussions

After Synthesis 0% device utiliztaion

Altera_Forum
Honored Contributor II
‎03-06-2012 05:19 AM
1,375 Views

Hai after synthesis i got an RTL but quartus summarize 0% device utilization eventhough i have got all the components that i intended 

 

Please help  

Thanks in advance 

Aneesh R
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎03-06-2012 07:48 AM
348 Views

This means that the synthesisor has "optimised away" your entire design. This could be for many reasons. 

 

1. No Inputs or outputs connected 

2. Clock stuck at '0' or '1' 

3. clock enable stuck at '0' 

4. reset held at '1' 

 

So check your design for these conditions.
0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎03-06-2012 08:57 AM
348 Views

I am developing an 8-bit procesor IP core. I will check the above conditions 

Thak u very much
0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.