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Agilex DP IP integration with F-tile PHY some signals mismatch

HongLiang
Beginner
500 Views

We try to build a DP Rx function in Agilex.

 

There are some  DP RX interface need to connect to F-tile PHY IP 

HLian17_0-1676541347793.png

 

we can not find them in the F-tile IP interface. 

 

We check the DP example 

We found the F-tile IP need to be modified manually for these signals to meet the DP IP.

HLian17_1-1676541720778.png

 

But the IP is a black box for us, we are not sure it could be modified correctly. 

Could any guild doc or patch file help regenerate the F-tile IP for DP RX? 

 

 

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ZulsyafiqH_Intel
Employee
441 Views

Hi Liang Hong,

 

Thank you for reaching out.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

Allow me some time to look into your issue. I shall come back to you with findings.

 

Thank you for your patience.

 

Best Regards,

ZulsyafiqH_Intel


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ZulsyafiqH_Intel
Employee
385 Views

Hi Liang Hong,

 

Apologize for the delayed response.

At the moment, for Agilex device, we have only 2 available design as below:

DisplayPort Intel FPGA IP Design Example for Intel Agilex F-tile DeviceDisplayPort Intel FPGA IP Design Example for Intel Agilex F-tile Device

 

However, we do have a documentation from another device that you can use as reference to create DP RX design, you may refer to below link for more information:

AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design - 1.5. Creating the RX-only Design 

 

I would like to clarify some information below:

 

Q1. Did you generate your design from design example?

 

Q2. Did you manage to compile the design? Any errors message or violation?

 

Q3. Could you share with us your .qar file?

 

Thank you.

Best Regards,

ZulsyafiqH_Intel

 

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HongLiang
Beginner
369 Views

Hi  

 

Q1. Did you generate your design from design example?

YES  please see https://community.intel.com/t5/Intel-Quartus-Prime-Software/Does-the-Agliex-F-support-Display-port-IP/m-p/1456902#M77329

 

Q2. Did you manage to compile the design? Any errors message or violation?

Yes 

HongLiang_0-1678102902989.png

 

Q3. Could you share with us your .qar file?

please see the attached file

 

we don't know how to regenerate the F-tile IP 

It's not a standard  IP file.

HongLiang_1-1678103143016.png

 

BR

Hong

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ZulsyafiqH_Intel
Employee
337 Views

Hi Liang Hong,

 

Thank you for your feedback.

Since both forum cases reported by you are similar and pointing to same issue, I would like to suggest to only keep one case open as tracking to avoid miscommunication.

I have replied your forum case in Case No.05751620  , however I will put same reply below:

 

I have checked and generated a design example from my end and I do not observe any error in compilation.

Allow me to share with you my design for you to test from your end.

 

Q1. Did you change any setting in the Design example?

 

Q2. Do you mind sharing the steps/procedure that you use to generate the design example?

 

Thank you. 

Best Regards,

ZulsyafiqH_Intel

 

 

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ZulsyafiqH_Intel
Employee
277 Views

Hi Liang Hong,

 

We have not heard feedback from you for quite some time.

As mention to you previously, since there is another forum case reported by you are pointing to same issue, I will proceed to transition this thread to community support to avoid miscommunication.

 

I will continue to support you via forum Case No.05751620

 

Thank you. 

Best Regards,

ZulsyafiqH_Intel

 

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