Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
17252 Discussions

Alarm clock code for verilog cannot compile

Altera_Forum
Honored Contributor II
1,979 Views

Hi, the attached file is the code that I created for alarm clock school project 

 

It keeps giving me the error 'near "end": syntax error, unexpected end'. I have tried many ways to readjust the codes but nothing is working. Please help. Thank you
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
1,245 Views

Seems to be syntax error. Can double check on the syntax or typo?

0 Kudos
Altera_Forum
Honored Contributor II
1,245 Views

That document is completely empty. It has three titles and nothing else, so how are we supposed to help? 

 

The error sounds like you have an 'end' statement without a 'begin' statement. Maybe check line 20943.
0 Kudos
Altera_Forum
Honored Contributor II
1,245 Views

document is empty, please reload it.

0 Kudos
Reply