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Altera Register Chain

druepy
Beginner
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Hello,

 

I'm a student at Georgia Tech. I want to do some timing analysis on flip-flop/register chains. I've read the relevant material for the two devices I have access to - a Cyclone 5 and a Stratix 4. But, even when I manually connect the registers together (top register's q port feeds the bottom register's d port) and constration location assignments, Quartus rearranges how this register works. Most of the time, the simulation is using the asdata port instead of the d port. Chip Planner also shows this transformation happening. This means, I can't actually do the timing analysis I'd like to do. Sometimes it will  instead use a lut to feed the flip flop's d port. Both of these situations are ones I'm trying to avoid.

I've attempted using generate statements to generate arbitrary shift registers and randomly used logic, but I'm guessing the fan-out is too low to force the router to use the register chain. There's very little information on this feature that's been advertised in multiple devices. I've found one other forum thread about this from 2010, but it didn't really solve anything.

 


Could a moderator provide clarification or a design for the Stratix 4 or Cyclone 5 that makes use the register chain? It's advertised, but I can't get it to synthesize.

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FvM
Valued Contributor III
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Hello,
not completely clear what you are trying to achieve. Generally speaking, Quartus will implement the logic according to your description. If the description is ambiguous, it may lead to unexpected result.
Please show your logic description (HDL/graphical) and describe in detail what you expect.
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Nurina
Employee
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Hi,


Quartus usually optimizes the placement & routing, sometimes it would even synthesize away part of your code. Perhaps that is what's happening in your case.

What is the purpose of this chain? Is it for synchronization, something like this? https://www.intel.com/content/www/us/en/docs/programmable/683082/21-3/synchronization-register-chains.html


Can you share the .qar file of your project so I can understand what's possibly causing the issue? To generate this, go to Project>Archive Project.


Regards,

Nurina


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druepy
Beginner
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Hello,

 

I called it register chaining, but it appears the datasheet calls it register cascading.

 

My approach has been to exhaust local system resources to force Quartus to have to utilize the register cascade connection.

I've tried a few different approaches. One approach is to use extended_lut's to use the majority of the ALM inputs to prevent Quartus from being able to utilize the connections to ASDATA. I combined this with an exclusion_list in the rcf. This caused a fitting error.

I've also use Verilog Generate statements to force a ton of logic cells to be used as well as flip flops. That didn't show anything.

I then attempted the same thing, but with ALM's that use the adder. This also had the same error. I searched our repository of designs and also didn't see this utilized anywhere; including some very resource intensive designs. I'm starting to think there's a bug in Quartus preventing this, but this hasn't been stated in the errata. It's also very heavily advertised for multiple chips, so I'm unsure why it's so difficult to get Quartus to do this.

 

I've attached my qar file.  I appreciate the help.

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Nurina
Employee
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Thank you for attaching your design. Can you let me know which version of Quartus you are using?


Regards,

Nurina


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druepy
Beginner
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I have access to several versions after 17.0. I've tried 17.0, 17.1, and 22.1. All of them have the same issue.

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Nurina
Employee
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Hi,

 

Is this what you're trying to achieve with the design you shared?

Nurina_0-1687505180518.png

 

I removed the location assignments set to reg_out* so it is able to run fitter- they're set too close to lc* signal locations so routing failed. If you don't want your registers to be retimed, setting location assignment is not the right way. Instead, you should use the Netlist Optimization setting to "Never Allow" : https://www.intel.com/content/www/us/en/docs/programmable/683230/18-1/preventing-register-movement-during-retiming.html

 

You may also find this useful: https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir.htm

 

Regards,

Nurina

 

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druepy
Beginner
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That's functionally what I'm trying to do.

 

The specifics are that I'm trying to avoid it using normal routing. The handbooks talk about register cascading. In Chip Planner, that should show a direct connection between the to FF in an ALM and the bottom FF in an alm.

 

I just did a quick glance at that first link you sent me. It mentions the cascade chains; I'm specifically trying to get a design that utilizes a cascade chain so I can measure the (likely minute) differences between the different methods Quartus uses to route. Are  your modifications synthesizing a cascade chain?

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druepy
Beginner
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I just made the changes you suggested, and Quartus just isn't using the register cascade that it's supposed to be able to do. I kind of just want any design that can use a register cascade; I can reassign any IO so I can take my measurements. But I'm just trying to get this one specific mode. It's mentioned so many places, but it seems near impossible to get Quartus to synthesize and make those decisions.

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_AK6DN_
Valued Contributor II
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FWIW it is not that uncommon for hardware engineers to design in some features that they thought were really neat or useful and that the downstream software guys never figured out a way for a compiler to use in any reasonable way. Happens frequently in CPU instruction set designs, I would not at all be surprised that it happens in FPGA macro cell design. It may very well be there is no way to convince Quartus to use that feature automatically. Or maybe there is just one archaic use case. You would probably need to talk to the Quartus implementers that are responsible for the mapping/layout algorithms to tell you what that use case is.

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druepy
Beginner
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Your answer is reasonable, however I don't quite find it acceptable in this given context. The handbook is an advertisement of the features the chip offers and reasons to use them. Why would you want to force this issue? I'm not sure, but I'm tasked with measuring this for a research paper. This feature has been advertised for over 20 years; this is quite astounding.

 

Because of this thread I've decided to find some old archived datasheets and handbooks. Stratix, Stratix 2, Stratix 3, Stratix 4, Cyclone 3, Cyclone 4, Cyclone 5. I see that it seems starting with the Arria V, the handbook no longer advertises this ability. The Cyclone 10 LP does advertise it, but the Cyclone 10 GX does not.

 

 

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druepy
Beginner
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My edited response didn't come through.

 

I'm starting to draw the conclusion you proposed -- hardware guys added it but software guys didn't enable it. It's just that the handbook then shouldn't have advertised this feature  over the years. I was also hoping that an employee might have access to be able to confirm that this was the case.

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Nurina
Employee
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Hi,


You mentioned a datasheet- can you share it here?


Regards,

Nurina


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druepy
Beginner
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Here you go.

 

Page 2-17 specifically is what I'm looking at, but other diagrams in this chapter show this connection.

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Nurina
Employee
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Hi,


I'm not familiar with register cascade on Stratix IV. On the chip planner and timing analyzer I am seeing that it is not a direct connection as you have described, I'm not sure if this is how it's suppose to be. Do you know how to check if it's a register cascade?


I'm trying to check if this is something that should be set in the qsf.


Regards,

Nurina


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Nurina
Employee
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Hello,


Do you have any updates?


Regards,

Nurina


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Nurina
Employee
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Hi,


I can't seem to find any setting to enable this.


From a past case it seems that using location assignment as you have previously done solves the problem.

I tried below and it seems to show the path of a register chain:

set_location_assignment MLABCELL_X1_Y55_N2 -to reg_out[0]

set_location_assignment MLABCELL_X1_Y55_N4 -to reg_out[1]

set_location_assignment MLABCELL_X1_Y55_N6 -to reg_out[2]

set_location_assignment MLABCELL_X1_Y55_N8 -to reg_out[3]

set_location_assignment FF_X1_Y55_N1 -to ff0

set_location_assignment FF_X1_Y55_N3 -to ff1

set_location_assignment FF_X1_Y55_N5 -to ff2


Regards,

Nurina


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druepy
Beginner
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Thank you for working on this.

If chip planner shows the register chain path for you, would you be able to screenshot chip planner on your system and also send me the project?

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Nurina
Employee
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Here is the screenshot and .qar file as requested.

Nurina_0-1688695808837.png

I used 22.1std.

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druepy
Beginner
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I won't be able to use the qar until Monday. Could you double click on that middle lab element and screenshot that for me?
I can reproduce this, but when looking at the more detailed view it shows that it's not using that register cascade connection the handbook advertises.

 

I really do appreciate you spending time on this.

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Nurina
Employee
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Also, I used ff* instead of lc* because that's part of the data path as shown in timing analyzer:

Nurina_1-1688695982740.png

You can also see that the location setting I had set are reflected on here.

 

Regards,

Nurina

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