Are Unpacked Array Supported in Platform Designer's Component Editor?

[TuckerZ]

Hello, 

I'm trying to design an Avalon MM Slave and turn it into a component for use inside of platform designer using the component editor. 

In my top level HDL file, I have these two ports which are multidimensional. They are both unpacked arrays of vectors

input   logic [AVALON_BUS_WIDTH - 1 : 0] coe_status_reg [NUM_STATUS_REG - 1 : 0],
output logic [AVALON_BUS_WIDTH - 1 : 0] coe_control_reg  [NUM_CONTROL_REG - 1 : 0]

I load the appropriate HDL file into Synthesis Files section of the Component Editor's Files tab. When analyzing synthesis files, I run into these errors.  

Error: Verilog HDL or VHDL XML Interface error at avalon_mm_adapter.sv(46): port "coe_status_reg" has an unsupported type File: /users/223063335/documents/projects/xxx/hdl/hdl/avalon_mm_adapter.sv Line: 46

Error: Verilog HDL or VHDL XML Interface error at avalon_mm_adapter.sv(58): port "coe_control_reg" has an unsupported type File: /users/223063335/documents/projects/xxx/hdl/hdl/avalon_mm_adapter.sv Line: 58

 My questions are:

1. Is the unpacked dimension causing this error? 
2. Is it possible to have a multidimensional array as a port in the Component Editor. 
3. If the answer is yet to Q2, how do I resolve this error? 
4. If the answer is no to Q2, how can I get around this without hardcoding the number of ports I need? 

[sstrell]

Where are these parameter values defined?  Will the user of this component be able to set them?

[TuckerZ]

These parameters are defined in the port list. The component editor has detected them as parameters. 

module avalon_mm_adapter 
    #( 
        parameter   AVALON_BUS_WIDTH    = 32,
        parameter   NUM_CONTROL_REG     = 1,
        parameter   NUM_STATUS_REG      = 1  )
    (
        input   logic           csi_clk,       
        input   logic           rsi_n,     

        // Avalon Bus Signals
        input   logic [AVALON_BUS_WIDTH - 1 :0] avs_writedata,
        output  logic [AVALON_BUS_WIDTH - 1 :0] avs_readdata,
        input   logic [AVALON_BUS_WIDTH - 1 :0] avs_address,
        input   logic                           avs_read,
        input   logic                           avs_write,
        output  logic                           avs_waitrequest,
        output  logic                           avs_readdatavalid, 

        // non-Avalon Signal
        input   logic [AVALON_BUS_WIDTH - 1 : 0] coe_status_reg [NUM_STATUS_REG - 1 : 0],

        // control outputs to fabric 
        output logic [AVALON_BUS_WIDTH - 1 : 0] coe_control_reg [NUM_CONTROL_REG - 1 : 0]
    );

[RichardTanSY_Intel · Accepted solution]

May I know which version of Quartus are you using, Standard or Pro?

I'm afraid that if you are using Quartus Standard, there is limited support for the System Verilog language.

Link: https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/verilog-and-systemverilog-synthesis-support.html

The recommendations are as follows:

1. Upgrade to Quartus Pro.
2. Modify the design code by converting the multidimensional arrays into single-dimensional arrays.

Unfortunately, the engineering team has no plans to enhance Quartus Standard.

We apologize for any inconvenience caused by the limitations of the tool.

Best Regards,

Richard Tan

Edited: Platform Designer does not support 2D arrays. 

[TuckerZ]

I am using Standard Edition.

However, it seems that Quartus Prime can handle a multidimensional port like this when just including this file outside of platform designer and elaborating it there. The problem presents itself when trying to use platform designers component editor. Are the requirements/capabilities between the two different?  

[RichardTanSY_Intel]

Yes, they may indeed different, as they serve different purposes within the Quartus Prime software.

Best Regards,

Richard Tan

[TuckerZ]

Thank you for the information, however unfortunate. 

Another question then: Where can I log a request for improvements to Quartus Prime Standard Edition?  

[RichardTanSY_Intel]

We can assist you in submitting the enhancement request, but please note that the chances of the enhancement being accepted for Quartus Standard are minimal to none.

It's important to mention that our resources primarily focus on Quartus Pro, where enhancements are more likely to be considered and implemented.

We appreciate your understanding in this matter.

With that in mind, I will proceed to submit an enhancement request for this issue.

Please let me know if you have any further questions before we close the case. 

Best Regards,

Richard Tan

[RichardTanSY_Intel]

I regret to inform you that the engineering team is unable to provide support for enhancement requests for Quartus Standard.

Therefore, I must inform you that the request for SystemVerilog support in Platform Designer has been rejected.

However, please note that if you have an enhancement request for Quartus Pro, we would be more than happy to assist you.

Feel free to reach out to us with any such requests or any other inquiries you may have.

Thank you for your understanding in this matter.

If you have any further questions or require additional assistance, please do not hesitate to let us know.

Best Regards,

Richard Tan

[RichardTanSY_Intel]

Thank you for acknowledging the solution provided. With that, I will transition this thread to community support.

Thank you and have a great day!

Best Regards,

Richard Tan