Alternative to weak pull-up for I/O during configuration?

[Altera_Forum]

Hello, 

 I've got the following problem:   I use a Cyclone II FPGA in a complex design. Some User I/Os are connected to npn transistors. The problem is, that during configuration thru an epcs4 device the outputs are weak pull-up. This means, that the npn transistors connected to these outputs are conductive during configuration (circa 260ms). The Design works properly on a ready developed PCB, but the Quality Management in my Company does not allow these transistors to be conductive during power-up. It is also not possible to add some pull-down resistors, because the PCB design should not be changed.   Is there any possibility to pull-down the USER I/O Pins during configuration? Maybe a little tick in Quartus settings?   I hope somenone knows what I mean and has a solution!   Thanks in advance   Stefan   PS: Sorry for my bad english!

[Altera_Forum]

In unconfigured state, the device didn't yet receive any configuration data. How should Quartus be able to change the device behaviour then? the weak pull-up mechanism is hardwired in fpga silicon only. 

 An external pull-down resistor is a simple and reliable method to achieve the required behaviour. The weak pull-up resistor range is given in device manual (10 k minimum for most devices), it's easy to calculate a suitable pull-down resistor dimensioning.

[Altera_Forum]

Hi FvM, 

 Thanks for your reply! I've expected that there´s no way to change the USER I/O behaviour during configuration! I think I have to make a redesign of the PCB to achieve the behaviour I need. Unfortunately it´s not possible to solder some additional pull-down resistors on the PCB, because the transistors are in a SOT 363 Package. Maybe it´s possible to add some external inverters on the pcb and change the vhdl file to change the behaviour.

[Altera_Forum]

You can use dual transistors with integrated resistors or solder 0201 chips to the SOT363 pins.

[Altera_Forum]

Is there any reason why newer devices don't use Bus-Hold during config, instead of weak pull-up?

[Altera_Forum]

Bus-hold hasn't a defined initial level, it would be unacceptable for many applications.

[Altera_Forum]

--- Quote Start ---  Bus-hold hasn't a defined initial level, it would be unacceptable for many applications.  --- Quote End ---    I am talking at POR & config time, before user mode. Why you would care at all about a defined level before user mode?

[Altera_Forum]

I seriously care about it, cause I have hardware connected to some I/O pins that may be instantly damaged when receiving illegal signal patterns.

[Altera_Forum]

--- Quote Start ---  I seriously care about it, cause I have hardware connected to some I/O pins that may be instantly damaged when receiving illegal signal patterns.  --- Quote End ---    I see. You are using the weak pull-ups, not for the purpose of avoiding floating inputs on the FPGA, but also for providing a defined power-up output level.  I assumed that in those applications where the power-up level is critical, an external pull-up or pull-down would be used, but I guess I was wrong.

[Altera_Forum]

Today I talked to an FAE from my distributor and he told me that possibly in Cyclone IV devices it might be possible to choose between weak pull-up and weak pull-down I/Os during configuration. A special PIN has to be hard-wired for selection, but these are plans for the future. I think I'll leave my design unchanged because it works well. In a re-design of the PCB I use some unused inverters to meet my requirements. 

Thanks for your suggestions! Stefan