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Altpll using output frequency

Altera_Forum
Honored Contributor II
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Dear, 

 

When compiling a simple project with the attached pll as a toplevel i get the following error because i try to use output frequence parameter in stead of device and multiply parameters. 

Q9.1--> Error: PLL "altpll:altpll_component|altpll_ign2:auto_generated|pll1" has port CLK[0] connected but parameters clk0_multiply_by and/or clk0_divide_by are either unspecified or set to 0 

 

I really want to define the output frequency in stead of devision and multiply factors. 

 

Can somebody make this work? 

 

Thx, 

Johannes 

 

more info: 

 

I want to create a pll based on a vhdl file not using the gui because I want to do batch compilation of pll's with different output frequency settings. 

 

This is what i did: I started from a megawizard generated file. The project compiles fine. I looked in the autamtically generated file and saw that a clock devision and multiplier parameter was created (although is specified a frequency in the megawizard): 

clk0_divide_by : NATURAL; 

clk0_multiply_by : NATURAL; 

 

I'd like to work with the output frequency parameter instead as stated in the "The Phase-Locked Loop (ALTPLL) Megafunction User Guide"  

 

"CLK[]_OUTPUT_FREQUENCY: Integer:  

Specifies the output frequency of the corresponding output clock port, CLK[9..0].This parameter is ignored if the corresponding CLK[9..0] port is not used. This parameter is unavailable if multiplication or division factors are specified. If omitted, the default is 0." 

 

When compiling a simple project with the attached pll as a toplevel i get the following error: 

--> Error: PLL "altpll:altpll_component|altpll_ign2:auto_generated|pll1" has port CLK[0] connected but parameters clk0_multiply_by and/or clk0_divide_by are either unspecified or set to 0 

 

I guess it has something to do with the statement in the user guide at the devide/multiply paramerters: 

"Specifies the integer division factor for the VCO frequency of the corresponding output clock port, CLK[9..0] port. The parameter value must be greater than 0. Specify this parameter only if the corresponding CLK[9..0] port is used; however, it is not required if a clock settings assignment is specified for the corresponding clk[9..0] port. If omitted, the default is 0." 

 

What Clock Settings assignment???? 

 

Kind regards, 

Johannes
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Altera_Forum
Honored Contributor II
1,261 Views

You didn't clarify, if you manually edited the MegaFunction generic parameters or if the wizard generated file causes an errot in Quartus compilation?

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Altera_Forum
Honored Contributor II
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The megawizard generated file compiles fine, but it uses the multiply and devide parameters in stead of the output frequency parameter. 

 

When i try to adapt the generated file manually (as in the attached file) it goes wrong. I simply ommit the clk0_divide_by and the clk0_multiply_by parameters and replace it with the clk0_output_frequency parameter and it fails to compile. 

 

Regards, 

Johannes
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Altera_Forum
Honored Contributor II
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Judging by your own work I can say: 

 

The frequency parameter need to be converted to PLL parameters of mult/div and not the other way round. PLLs ar based on these figures for their internal counters. Frequency entry is just a user convenience. 

 

You will need to convert frequency manually to mult/div factors if you don't want GUI. Remember not all frequencies are possible. Only those that fit the mult/divide values.
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Altera_Forum
Honored Contributor II
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I agree, that according to the MegaFunction user manual the clkx_output_frequency parameter should work, but it seem to be unsupported. I wasn't aware of, because I'm using mutiplier/divider also in manual PLL instantiation.

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Altera_Forum
Honored Contributor II
1,261 Views

Dear, 

 

Thx for the effort, I think i worked it out. 

 

You can use clkx_output_frequency parameter IF you define the multiply and devision factors in the SDC file. Make a clock and derived clock for the pll clocks.  

 

It seems that one needs either way to supply Quartus with multiply and devision factors. So i have to agree with kaz and calculated myself the mult and div factors. This is not so easy as it seams because their are a lot of restricions eg. Fvco max/min, m max, n max, c max,.... And it is frustrating because i know Quartus CAN do it (it does it in the megawizard GUI!). Not very convenient for the user :-( 

 

Anyhow: if their are more tips to tackle this problem in an elegant way just add them to this tread! I will be gratefull. 

 

Have a nice old to new! 

Johannes
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