Analysis & Synthesis was canceled due to an error

[Altera_Forum]

After running synthesis for about a minute, I saw this pop-out message, "Analysis & Synthesis was canceled due to an error (68 warnings)", which stopped my synthesis. However, when I checked the error/warning/message window below, it did not specify an error, i.e. the error message window is empty. The last info message is: 

"Info: Found 1 design units, including 1 entities, in source file ../src_rtl/ehi/gmac/gmac_ip/mmc/DWC_gmac_mmc.v  Info: Found entity 1: DWC_gmac_mm". Anyone knows or has good suggestion as to why my synthesis could not proceed?

[Altera_Forum]

Somewhere in the processing printout is the actual error message. Click on the "Errors" tab to show just the errors. 

 Jake

[Altera_Forum]

i have tried that, but nothing shows up in the "Errors" tab

[Altera_Forum]

--- Quote Start ---  i have tried that, but nothing shows up in the "Errors" tab  --- Quote End ---    Hi Fred,  was it the first time youn run the synthesis for your design and which Version of Quartus did you use ?  Kind regards  GPK

[Altera_Forum]

If I understand right, the compilation is cancelled with zero error count? If so, it must be regarded as a compiler bug. You should forward a design, that reproduces the problem, to Altera support. 

 P.S.: It's always a good idea to reset the design by deleting the db directory.

[Altera_Forum]

--- Quote Start ---  Hi Fred,   was it the first time youn run the synthesis for your design and which Version of Quartus did you use ?   Kind regards   GPK  --- Quote End ---     I have been running and finishing synthesis for the same design a few times, but we made a major change in code by adding some new files and now it won't synthesize. I am using Quartus II 9.0. Just wonder if there is an obvious reason why synthesis stopped without showing an error

[Altera_Forum]

--- Quote Start ---  Just wonder if there is an obvious reason why synthesis stopped without showing an error  --- Quote End ---  Most likely not obvious. The issue may be trigerred by a design error or a design detail unexpected by the compiler. You can try to identify it by rolling back the design changes. And if you found the step, that introduced the error, to dissect it further.

[Altera_Forum]

It turns out in my .qsf, a directory path got specified as a verilog file during the "set global_assignment" statement. I had a script auto-generating the content of .qsf. 

I wonder why the compiler wasnt smart enough to report that

[Altera_Forum]

I would venture a guess that you may be the first person in history to have done such a thing. Altera probably never thought of it as a possible scenario. You should file an SR either through the FAE or the Altera website.